Sorry - didn't had too much time for developing different test utilities.
This is the first step.
It has a simple program which checks if ROM addressing is working properly in a ZXmore.
In the ZIP there is ZXMDIAG2.ROM which may be flashed on a ZXmore to any instance (except 0).
It will be placed in instance 2 later for an official diagnostic ROM.
The ZIP contains also a 512k BIN file which may be burned to the flash ROM through a eprom burner for those system really need this diagnostic ROM and are not able to flash the internal ROM. The complete diagnostic ROM will be delivered from release 1.9 on and contains following content:
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0=ZXmaster
1=ZX81
2=DIAG2 (rom)
3-6=ZX81
7=ZX80
As reading the ROM is the most essential part this is completely separated from other test routines and does not require access to RAM. So this test will even work when RAM is bad or not present. It is most simplified and contains a routine which runs in an endless loop. All code is in address area $0000-$00FF and non used areas are initialized with a HALT ($76) while interrupts have been disabled and NMI turned off directly after startup. So whenever a wrong address is executed or a NMI happens the CPU will be halted forever (except repeated NMI's which can be detected with a scope or logic analyzer).
This is the code:
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format zx81 as 'rom'
define NEWLINE $76
define IOADRKBD $FE // io address, keyboard check
define IOADRNMION $FE // io address, NMI on
define IOADRNMIOFF $FD // io address, NMI off
ORG $0
OUT (IOADRNMIOFF),A
DI
LD A,$FF
JP pre
db $7C-$ dup(NEWLINE)
pre:
LD R,A
OUT ($FF),A
main:
db $20 dup(0)
JR pre
db 2000h-$ dup(NEWLINE)
This should be measured at CPU:
NMI (pin 17) = high
HALT (pin 18) =high
IORQ (pin 20) = one pulse (OUT instruction) every 25us (assuming 6.5 MHz clock), 400ns width, repeated
WR (pin 22) - same as IORQ (due to the OUT instruction)
A15 - A8 = one pulse every 25us (together with IORQ), 600ns width, repeated
IORQ should be used as trigger signal on one channel while displaying one of the other signals at the other channel.
Choose horizontal resolution of 2us/div and expect following pattern on the address lines:
A0 = toggling every 600ns (16 low and 16 high pulses alternating, = 32 nop instructions, instruction address and refresh address synchronous)
A1 = toggling every 1.2us (8 pulses like above, double length)
A2 = toggling every 2.4us (4 pulses)
A3 = toggling every 4.8us (2 pulses)
A4 = toggling every 9.6us (1 pulse low and 1 pulse high)
A5 = low for about 9.6us
A6 = low for about 9.6us
A7 = high for about 9.6us
M1/RFSH same as A8 while M1 starts with low and RFSH starts with high
ROMCS (IC4, pin 22) = low for about 9.6us (32 small needle pulse high may be seen)
OE (IC4, pin 24) = low for about 9.6us (32 small needle pulse high may be seen)
So this will be continued but I am now on a business travel for about one week.
Next step will be testing RAM access.
If the signals are measured the ROM access seem to work properly.
Standby alert 
