64 Column Zeddy.... Well maybe...

[siggi]

patchinh the save routine is easy, the load routine not so easy how does one double $9f in a single byte

Why not switch back to normal clock during SAVE and LOAD (and PRINT)?

Siggi

[siggi]

and pin 16 of the CPU is bent out so that it misses the socket (INT pin) as R is loaded with values that already have bit 6 reset, so a new INT signal is generated when A6 = low, HALT = low, refresh = LOW, this avoids an int happening early on in the scanline, this is why i was going to leave this little side project because i couldn't at first see a simple way around this problem.

Perhaps you could let the INT be disabled and put an EI into DFILE (just before the HALT) to enable the INT only at the end of the line?

Siggi

[Andy Rea]

Yeah might, do the switching clock speeds again !, but i think it might be possible to add a single NOP into the timing loop that will allow a timer count < $ff to be used.

Adding an EI before the HALT ? woudl require some extra patching...

Andy

[siggi]

Wilf Rigter did not have HALTs in the DFILE of his NOVA program. So he had 34 chars/per line and 68 chars might be possible with some more patches

Siggi

Edit: Link: http://www.user.dccnet.com/wrigter/inde ... va2005.htm

[Andy Rea]

I guess anything is possible with a custom Video routines, even maybe true interlace... but not entirely sure since as you need quite timing to get the monitor/tv to recognise odd/even frames.

This way is hardly modified the ROM, just added a small delay routine, and changed a few values.

Andy

[PokeMon]

Adding an EI before the HALT ? woudl require some extra patching...

Andy

I think this is a quite interesting idea and will solve the A6 problem.
EI has bit 6 set and will be executed normally from CPU and disable ULA char interpreting.
So background will be hold "white" and CPU can execute first EI and second following HALT.

[gammaray]

Is this idea dead. (Idea is 3/4 dead)

http://forum.tlienhard.com/TS1000/www.t ... 885555.htm