ZX81 ULA-in-a-CPLD

Any discussions related to the creation of new hardware or software for the ZX80 or ZX81
commie
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Re: ZX81 ULA-in-a-CPLD

Post by commie » Tue Nov 22, 2016 5:55 pm

PokeMon wrote:
commie wrote:
PokeMon wrote: It would be interesting to see what happens when switching NMI on and off if this brings your system to crash even if NMI is not connected and so NMI can not occur from sight of the CPU. Up to you - just a proposal if you are interested in solving this problem. If not, is okay for me. ;)

PokeMon,

I will try your test very soon(it's more ammo-thanks), I have never heard of 'powerbasic' for the zx81 before you brought to my attention, thanks for the link but please, I rate your input very highly and thanks so far, I appreciate you very much.
Right now I have some chips that have arrived by post and using them I want to extend my zx81 prototype from 16k to 32k in fast mode of course. :D

Cheers
Commie

commie
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Re: ZX81 ULA-in-a-CPLD

Post by commie » Tue Nov 22, 2016 8:49 pm

Hi Folks,

Just some extra info which might help, the t state synchroniser which is a npn bjt emitter=nmi, collector (via 1k resistor)=cpu wait and base (via 10k resistor)=halt. If I remove the halt 10k base resistor then wait states are no longer activated, with this resistor out of circuit, I get a corrupted inverted K cursor(pixel related) and the system is running in slow mode, pressing 'print' gives corrupted print on the screen(pixel related), which tells me the cpu is running successfully in slow mode.The top right hand corner of the screen is also corrupted.

Cheers
Commie

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PokeMon
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Re: ZX81 ULA-in-a-CPLD

Post by PokeMon » Tue Nov 22, 2016 10:14 pm

Could you post this schematic detail and type of transistor ?
If the WAIT function is not active there is no synchronization of the picture which could be seen in the top line but normally should have been solved till the cursor line on a normal TV. Typically there is a mismatch between start of horizontal sync but this is normally solved with about 2 pixels from pixel line to pixel line.

Which type of display are you using ? Is it a CRT monitor or a flatscreen (LCD) ?
Is the horizontal sync generator creating a pulse every 64us ? 15.625 kHz ?
The FAST mode display is quite different and fully handled in software - so a timing mismatch in horizontal sync is not seen in FAST mode in general.

commie
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Re: ZX81 ULA-in-a-CPLD

Post by commie » Wed Nov 23, 2016 12:35 pm

PokeMon wrote:Could you post this schematic detail and type of transistor ?
PokeMon,
I don't have the schematic in a file right now but look on any zx81 schematic and locate Tr1, the transistors I've tried are PN2222A and 2N2369A, both give the same results, I have also varied the relavent resistor values to exhaustion.
PokeMon wrote: Which type of display are you using ? Is it a CRT monitor or a flatscreen (LCD) ?
LCD, the compasite videa/sync comes straight out on a cpld pin and through 2x diode drop into the LCD monitor.
PokeMon wrote: Is the horizontal sync generator creating a pulse every 64us ? 15.625 kHz ?
Yes, generates 15.702KHz sync pulses.

This morning I built a ram chip select circuit using a couple of gates in order to free up one pin on the cpld and also to test whether cpu clock discrepancy is an issue?, this done it made no difference whatsoever, in other words my original clocking scheme is sound and no longer a doubt.

Cheers
Commie

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PokeMon
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Re: ZX81 ULA-in-a-CPLD

Post by PokeMon » Wed Nov 23, 2016 8:58 pm

commie wrote:
PokeMon wrote:Could you post this schematic detail and type of transistor ?
PokeMon,
I don't have the schematic in a file right now but look on any zx81 schematic and locate Tr1, the transistors I've tried are PN2222A and 2N2369A, both give the same results, I have also varied the relavent resistor values to exhaustion.

Cheers
Commie
Did you use the 47pF capacitor in parallel to the 10k resistor as well ?
It seems that the transistor doesn't switch fast enough and is probably saturated.

commie
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Re: ZX81 ULA-in-a-CPLD

Post by commie » Wed Nov 23, 2016 9:15 pm

PokeMon wrote: Did you use the 47pF capacitor in parallel to the 10k resistor as well ?
It seems that the transistor doesn't switch fast enough and is probably saturated.
I tried a whole range of capacitors and resistors, also I built the circuit using an 'or' and inverter gates and still just the same result.

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RetroTechie
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Re: ZX81 ULA-in-a-CPLD

Post by RetroTechie » Wed Nov 23, 2016 11:24 pm

commie wrote:2. Again, with your hsync generator, your syncro counters have 'chip enable'(ce), it looks like an ls161 ttl counting scheme?, so what I did was, second syncro counter is clocked with tc(terminal count) from the first syncro counter which is clocked with 3.25MHz cpu clock. The hsync/back_porch and reset logic remain the same except on your back_porch you are gating tc?, I removed it.
IIrc that's "clock enable" but is kinda the same thing in this context.. ;)

I was wondering though: in a ZX81 the hsync pulses come at 207-cycle intervals. Logic decoding the counter bits just decide where in the 207-cycle period hsync and back porch are active. Could you post the exact logic you're using to decode these 2 signals? (as a function of that 207-cycle's count value). Maybe there's something in there we're overlooking.
Just some extra info which might help, the t state synchroniser which is a npn bjt emitter=nmi, collector (via 1k resistor)=cpu wait and base (via 10k resistor)=halt. If I remove the halt 10k base resistor then wait states are no longer activated, with this resistor out of circuit, I get a corrupted inverted K cursor(pixel related) and the system is running in slow mode, pressing 'print' gives corrupted print on the screen(pixel related), which tells me the cpu is running successfully in slow mode.The top right hand corner of the screen is also corrupted.
That's a question I didn't see fully answered so far: does the machine hang always when NMI's are passed through (no matter what else you do), or is it screen corruption only? Why this matters:

There's quite a few things that can go wrong in an ULA implementation like this. BUUUTTT... much of that affects screen output only. Shift register, when pixel data is grabbed from databus, invert bit, etc. The Z80 doesn't care & will execute programs (or forced NOPs) as usual. With 2 exceptions:
  • /ROMCS and /RAMCS (and related to them, that "stretch" signal in my CPLD design). If this were messed up, chances are FAST mode wouldn't work reliable either. Or you'd have no sensible looking screen output at all. So I think this part is working.
  • /NMI output to the Z80. That signal has the potential to cause a hanged CPU. For example when a NMI is received while Z80 is just processing a NMI: if I'm not mistaken, NMI's are basically handled as CALLs (with a special effect on Interrupt FF's), so nested NMI's could cause the machine to run out of stack space / stack overwriting system variables or similar.
What also may help is posting a few screenshots... sometimes what's going wrong is right there to see on screen.
Bitcycle.org - just flipping bits

commie
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Re: ZX81 ULA-in-a-CPLD

Post by commie » Thu Nov 24, 2016 7:05 pm

RetroTechie wrote: IIrc that's "clock enable" but is kinda the same thing in this context.. ;)
Okay yeah kinda the same thing but it makes more sense now because it just means the clock is gated with ce.
RetroTechie wrote: I was wondering though: in a ZX81 the hsync pulses come at 207-cycle intervals. Logic decoding the counter bits just decide where in the 207-cycle period hsync and back porch are active. Could you post the exact logic you're using to decode these 2 signals? (as a function of that 207-cycle's count value). Maybe there's something in there we're overlooking.
That's correct, my hsync generator is identical to yours except loose /tc on your back porch. My tc from my first counter is simply fed into the clock input of the second counter. tc active transitions occur every time the first counter's count passes through zero.

Okay, more to come, I'm going to play around with my camera and see if I can get some screenshots. I'd also just like mention that my prototype now has a full 32kbyte ram and it's working.Tested it byte by byte. :lol:

CHeers
Commie

commie
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Re: ZX81 ULA-in-a-CPLD

Post by commie » Fri Nov 25, 2016 9:40 pm

Hi all,

Tested the nop generator today, agree's 100% retrotechie's timing diagrams perfect. :D

Cheers
Commie

commie
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Re: ZX81 ULA-in-a-CPLD

Post by commie » Sat Nov 26, 2016 2:01 pm

RetroTechie wrote: That's a question I didn't see fully answered so far: does the machine hang always when NMI's are passed through (no matter what else you do), or is it screen corruption only?
Hi Retrotechie,

The slow mode is quite unstable and so upon multiple global resets it falls on quite a few different states or screen characteristics, however, slow mode appears to partially work when the halt signal is removed from the t state syncroniser bjt. This done, it inhibits wait states signals getting to the cpu wait pin, the wait pin is then permanently high.The top right hand corner of the screen is corrupted and the inverted k cursor is somewhat corrupted but the cpu is running and there are nmi pulses going to the cpu. Also the you can type basic commands but they are corrupted or out of phase.

So to answer your question whether cpu hangs? yes if the t synchroniser bjt is connected as normal.

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