Simple UDG?

[mrtinb]

The char data can only be read from ROM.

Couldn't you just make a RAM expansion at 2000h-3FFFh that is accessed with ROMCS instead of RAMCS?

Wouldn't this make a UDG card with 16 custom fonts?

[Paul]

UDG doesn't require /ROMCS
It needs the lower Adress lines overridden by the ULA instead of just those from the CPU.
That's why the ram extension needs to be plugged in the ROM socket.
Kind regards Paul

[mrtinb]

Ok. Just a thought.

[Andy Rea]

There are ways to do external UDG

BUT none can be described as easy, although Wilf Rigters did a fairly easy one using a handful of TTL chips and an EPROM maybe the EPROM could be changed for RAM.

Andy

[gozzo]

aha, i worked out a possible way of doing that with wilf rigters external chr$ circuit, making it 'programmable', i never got round to building the thing to try it, if i can find the circuit (rough hand drawn) i'll scan it and post it here...

[mrtinb]

aha, i worked out a possible way of doing that with wilf rigters external chr$ circuit, making it 'programmable', i never got round to building the thing to try it, if i can find the circuit (rough hand drawn) i'll scan it and post it here...

Cool

[1024MAK]

If you look at the ZX81 schematic, you will see that both the data bus and part of the address bus (A0 to A8) have "isolating" resistors.
The address bus "isolating" resistors separate part of the ULA and ROM address bus from the CPU and RAM address bus. All this was done so that the display system works.

The important point being the part of the ZX81 display system, the video shift register (a parallel loading shift register in the ULA), that gets the pixel data of the characters, gets this data from the ROM by using a combined address made up partly from the CPU and partly from the address from the ULA. Hence address lines A0 to A8 are driven by the ULA. So the pixel data of the characters in a normal ZX81 screen has to come from a memory device connected to the ROM socket pins.

The detailed sequence of operations for each character byte is as follows:
1.    Each character code (CHR$) byte in DFILE is addressed by the CPU PC, on the rising edge T2 data is loaded from DFILE into the ULA: bits 0-5 into a 6 bit ULA address latch while bit 7 is loaded into 1 bit ULA video invert latch
2.    On the falling edge of T2, the ULA forces all CPU data lines to zero.
3.    On the rising edge of T3 the low data lines are interpreted by the CPU as a NOP instruction.
4.    During T3/4, the CPU executes the Refresh cycle and ROM address lines are generated with I register on A9-A15, the ULA 6 bit character code register on A3-A8, and the ULA modulo 8 line counter on line A0-A2.
5.    On the falling edge of T4, pattern data from the ROM is loaded into ULA video shift register and 8 video pixels are shifted out at 6.5MHz
6.    If character code latch bit 7 (in the ULA) equals 1, the video pixels are inverted.
7.    The CPU increments the program counter and fetches the next character code.
8.    This repeats until a HALT (Sinclair) is fetched.
9.    HALT opcode bit 6 = 1 and is therefore executed (no NOP).
10.           The ULA generates a HSYNC pulse independent of the CPU timing and the ULA LCNTR is incremented
11.           The halted CPU continues to execute NOPs, incrementing register R and samples the INT input on the rising edge of each T4.
12.           When A6, which is hardwired to INT, goes low during refresh time, (bit 6 of the R reg = 0), the Z80 executes the INT routine (below 32K)
13.           CPU returns from INT and resumes "execution" of DFILE CHR$ codes.
14.           The process repeats 192 times and then INT routine returns to the main video routine, turns on the NMI generator and switches back to the application code.

Link to on line article

The actual memory type does not matter. The dk'tronics and the various other "UDG" boards (all of which are very similar) have sockets for the ZX81 ROM, a EPROM with various fonts and provision for a RAM chip.

Mark

[nollkolltroll]

I built a stacked ROM/RAM with a 74-something on the side, that creates an 8k UDG area. Works fine, but still needs a handful of wires connected to the stack, so not a trivial build. There are guides out there for this type of expansion.