Hsync Timing

[cone]

The 3 D-FLIP FLIP that create the hsync . how does it create the sync pulse . do anyone have the actuall timing diagram? 14.5 cycle later after IOERQ low this is due to the INT ACK cycle . After that it goes lwo for 20 cycle? how does it does low 20 cycle ?after the 14.5 cylcle the sync will clear the left most D Flip FLop and it take only 2 M cycle to propergate to the right which will set the Sync high again? how is it 20 cycle?

[1024MAK]

I presume you are talking about a ZX80?

Grant’s page here describes the ZX80 circuitry. Does that help?

Mark

[cone]

HI

No it does not help I wanted to know the actual steps after the Int in triggered It will do into IINTACK cycle which will pull M1 low and IORQ low . This will preset the Left of the 3 D Flip Flop . Then what happen ? the 14.5 cycle will propergae the 1 from left to right which will pull the sync high . Then what happen next . How does it produce the 20 cycle 6 us Hsync ? can anyone help explain in details . cycle by cyle?

[cone]

Hi all


Maybe i try try describe my questions in more detail in Searle documentation on the Video Sync Generator

TV SYNC GENERATOR
Every INTACK (and I/O request) will preset the latch in IC 18. The display routine will halt the CPU until interrupted. It then generates an INTACK signal (/M1 and /IORQ low) which starts the sync generation. /M1 clocks the data through the two latches that eventually (14.5 cycles after IORQ going low) takes /SYNC low. The inverse (SYNC) output then resets the latch in IC 18 which is also clocked though this circuit, taking the /SYNC output high again after a short while. So, this circuit will generate a 20-cycle (6.15uS) low signal on the /SYNC line shortly after every I/O request. This 20-cycle sync is used for the horizontal syncs to the TV. In addition, the latch in the I/O decoder can force the output of the sync generator to be held low, as required for the longer vertical (frame) sync pulses on the /SYNC line.

It then generates an INTACK signal (/M1 and /IORQ low) which starts the sync generation. /M1 clocks the data through the two latches that eventually (14.5 cycles after IORQ going low)

the above i could understand that the INTACK have a extended m1 cycle and after then it takes around 13 clock and 2-Mcycle to move the 0 from

D flip flop 18 ( left) to 19 (right most) after that . Am right right to say that the sync going low will reset the Flip FLop 18 then will take another 2M cycle to propagate the high rom 18 to 19(right most) to bring the Sync signal to high so .

My question is this from the 2 M cycle generate 20 cycle? how ? which instruction is being run to generate the 20 cpu clock cycle . From the z800 document it will 13 cycle to reach 038h which is the flowing

Code: Select all

L0038:  DEC     C               ;; decrement the scan line counter in register C.
        JP      NZ,L0045        ;; JUMP to SCAN-LINE : repeats 8 times for each
                                ;; row of characters in DFILE.

        POP     HL              ;; point to the start of next DFILE row
        DEC     B               ;; decrement ROW counter
        RET     Z               ;; return if zero to

        SET     3,C             ;; load scan line counter with 08 was 00.
        
        ;; SCAN-LINE
L0045:  POP     DE              ;; discard return address

DEC C take 1 M Cycle 4 clock cycle
JP NZ take 2 M cycle 7 Clock Cycle
POP DE 3 M ccyle 10 clock

I cannot figure out how the 20 cycle is generated ?

thanks

[PokeMon]

Hi there.
It's allways tricky how Sinclair stuff works.

Attached is the listing as picture as you cut your listing in a particular point. The sync is triggered by INT ACK, in that point your are right. But then it is time delayed for 2 M1 cycles, resets the trigger and the duration is 2 M1 cycles again. So what happens ?

Hsync is triggered at INT ACK and becomes active at the second instruction in interrupt routine. This is the JP NZ which is always 10 clock cycles regardless if condition is met or not. The second instruction is a POP instruction with different registers which has also 10 clock cycles. Huuh - here we are. 10+10=20.

The interrupt routines are very clever in all points as the rest of the machine and in Sinclair stuff nothing is coincidence.

You can also calculate the delay of the HSync from the INT ACK condition. It is approx. 3.5 cycle as rest of INT ACK M1 plus 2 write cycles of the current address pointer so 9.5 cycles + 4 cycles for DEC C and so all in all 13.5 cycles delay if I am not really wrong. So there is a distinction between delay and duration. By the way there is only 2 wait cycles executed automatically (TWA), the next one in the timing diagramm (TW) is an example of an additional wait cycle but the ZX80/81 does not use/need additional wait cycles during video display.

Another story is WAIT used for sync of beginning of display routine together with NMI.