A0 to A6 address lines should always be changing state even if the processor is halted, as these pins also carry the refresh address (designed to refresh DRAM chips).
The data lines will only be at a valid logic level when being actually driven. In between instruction cycle fetches, or reads/writes to memory or I/O devices, the voltage will decay upwards or downwards (depending on a number of factors).
The important thing is not so much the actual signal. But looking to see if the highs are greater than 2V and the lows are less than 0.8V. And that they are changing state,
A14 and A15 determine if ROM or RAM are being addressed:
Code: Select all
A15 A14
0 0 ROM
0 1 RAM
1 0 ROM
1 1 RAM (when drawing the screen)
With the power off, you can test on resistance to test that all nodes (points/chips/components) are connected as per the schematic. Just keep in mind that some of the lines to the RAM are swapped around.
The normal electronic bench mats are what I use. They may be described as anti-static, but their resistance is so high, it won't affect a Zeddy. Alternatively use several layers of thin cardboard on top of a magazine or newspaper. Just make sure it's flat.
Mark