msknight wrote: ↑Wed Feb 21, 2024 5:55 am
I've compared the Hitachi chip against the half K chip read cycles and it looks like /OE is doing nothing. Looks like the whole thing is driven by the /CE and I should instead tie /OE to ground?
Or do I have that wrong?
Wrong.
/CE (/CS) when low selects the chip and if it has a lower power standby mode, 'wakes' it up. If /W (/WE) is high and /OE is high, it will not accept writes and will not drive the data bus.
If /OE is low at the same time as /CE (/CS) is low, it enables its data outputs. These being three state / tri-state outputs.
Yes, /OE could be connected to 0V/GND, but you don't gain anything, as normally the chips response to the /OE control input is quicker than that of the /CE (/CS) control input.
Some EEPROM/EPROM programmers can test SRAM chips like these. Although they may not test the access timing.
Mark