Search found 18 matches

by overCLK
Sun Nov 11, 2018 12:44 am
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 35199

Re: ZX81 ULA-in-a-CPLD

what i wanna know is what the heck is the ~IORQ line doing after the nmi stops... what in the world would cause so many io instructions ? how many lines has your logic analyser got ? i'm thinking about probing the entire data bus and ~m1 in addition to the other lines then you can decode the exact ...
by overCLK
Sat Nov 10, 2018 9:14 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 35199

Re: ZX81 ULA-in-a-CPLD

https://problemkaputt.de/zxdocs.htm#zx80zx81videodisplaytimings - see there. Strange, because: - I see 55 NMI pulses with US_UK pulled up in my British Zeddy and 31 before adding the pull-up. - I have seen this comment in ZX81 code disassembly (from here: https://www.tablix.org/~avian/spectrum/rom/...
by overCLK
Sat Nov 10, 2018 9:07 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 35199

Re: ZX81 ULA-in-a-CPLD

Gents, correct me if i am wrong, but there is no NMI generation at all when the ZX80_81 is pulled down. The quoted numer of 55 or 31 indicates how many scanlines should be generated and this value is read from ROM and held under the system variable called MARGIN. The MARGIN value is driven by the o...
by overCLK
Sat Nov 10, 2018 8:56 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 35199

Re: ZX81 ULA-in-a-CPLD

Gents, correct me if i am wrong, but there is no NMI generation at all when the ZX80_81 is pulled down. The quoted numer of 55 or 31 indicates how many scanlines should be generated and this value is read from ROM and held under the system variable called MARGIN. The MARGIN value is driven by the o...
by overCLK
Sat Nov 10, 2018 4:55 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 35199

Re: ZX81 ULA-in-a-CPLD

if you have the ability to program eeprom, then you could write some test code, simple loops repeatedly turning on and off the nmi, see if that turns up anything useful on the logic analyser. Yes, I can cook my own eeproms. I have made some custom ROMs before and the results were consistent (NMIs c...
by overCLK
Sat Nov 10, 2018 4:05 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 35199

Re: ZX81 ULA-in-a-CPLD

Thank you all a lot for suggestions and brainstorming.
I think I've already tried with an W27c512 EEPROM with the ZX81 ROM in. I'm not sure though. I will give it a try again just to be sure.
by overCLK
Sat Nov 10, 2018 1:41 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 35199

Re: ZX81 ULA-in-a-CPLD

1024MAK wrote:
Sat Nov 10, 2018 1:38 pm
Are you both using original Sinclair ROM chips?
If yes, which make / type?

Mark
I am. Marked as:
Sinclair Research 860 3PD.
D2364C 649
(C) 1981
by overCLK
Sat Nov 10, 2018 1:37 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 35199

Re: ZX81 ULA-in-a-CPLD

Looking at your snapshots, the NMI generation was re-entered successfully a few times and then stopped The is something weird going on. I think the same is going on in my case. Exactly. But I'm not able to find the condition that produces that. It is really interesting to know that something simila...
by overCLK
Sat Nov 10, 2018 11:19 am
Forum: Welcome Area
Topic: Hello from Spain
Replies: 9
Views: 820

Re: Hello from Spain

Hi Manuel, you#ll find it's mostly a happy place here, with happy people :lol: When he has recovered, Andy (a member here) may make some more of his replacement ULA modules. For more information have a read of this thread ;) erm yeah... honestly it's just laziness i have parts to build at least 20 ...
by overCLK
Sat Nov 10, 2018 10:26 am
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 35199

Re: ZX81 ULA-in-a-CPLD

Bear in mind that the main difference between ZX80 and ZX81 is this NMI generator. Disabling it via pulling ZX80_ZX81 line down, you block the NAND gate regardless of status of Hsync and NMI_on lines. Yes, completely agreed. The goal is to have it working in Slow Mode (i.e.: with NMI generation run...