Search found 1516 matches

by Andy Rea
Tue Jan 15, 2019 5:10 pm
Forum: Development
Topic: 3-lace
Replies: 8
Views: 630

Re: 3-lace

nollkolltroll wrote:
Tue Jan 15, 2019 11:27 am
A tip for viewing interlaced pictures, both standard and 3-lace: lower the contrast and brightness and the flickering will be reduced A LOT.
+1 thats how i took a picture :)
by Andy Rea
Sat Jan 12, 2019 8:01 pm
Forum: Development
Topic: 3-lace
Replies: 8
Views: 630

Re: 3-lace

very cool indeed, seems to work well with my 15" Sanyo b+w cctv monitor. Flickry as ever but hey oh...

Image
more pixels than you can imagine.

regards Andy
by Andy Rea
Sun Dec 09, 2018 9:41 am
Forum: Development
Topic: Tapestry wide
Replies: 6
Views: 427

Re: Tapestry wide

Brilliant stuff indeed, Shame the humble zeddy doesn't have sprites... Imagine some awesome scrolling action games...

Thanks for sharing this with us.

Andy
by Andy Rea
Fri Nov 30, 2018 8:10 pm
Forum: Hardware
Topic: Whats this?
Replies: 6
Views: 447

Re: Whats this?

interesting bit of kit, NO zx81 included in that auction.. think i'll pass

Andy
by Andy Rea
Thu Nov 29, 2018 1:07 am
Forum: Welcome Area
Topic: Pete editor of retrogamesmaster.co.uk
Replies: 3
Views: 290

Re: Pete editor of retrogamesmaster.co.uk

Welcome Pete, hope you enjoy learning about the quirks and tricks the little black door stopper has.

Mostly we don't bite, so any questions feel free to ask away.

Regards Andy
by Andy Rea
Sat Nov 10, 2018 9:23 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 30854

Re: ZX81 ULA-in-a-CPLD

what i wanna know is what the heck is the ~IORQ line doing after the nmi stops... what in the world would cause so many io instructions ? how many lines has your logic analyser got ? i'm thinking about probing the entire data bus and ~m1 in addition to the other lines then you can decode the exact i...
by Andy Rea
Sat Nov 10, 2018 8:54 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 30854

Re: ZX81 ULA-in-a-CPLD

McKlaud wrote:
Sat Nov 10, 2018 8:51 pm
well, this is not the case in my ULA, because I've got pull-ups and pull-downs there.
When you have eliminated the impossible, whatever remains, however improbable, must be the truth.

Sir Arthur Conan Doyle, stated by Sherlock Holmes.

strike that one then :) soon we will nail it down :lol:
by Andy Rea
Sat Nov 10, 2018 8:38 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 30854

Re: ZX81 ULA-in-a-CPLD

Gents, correct me if i am wrong, but there is no NMI generation at all when the ZX80_81 is pulled down. The quoted numer of 55 or 31 indicates how many scanlines should be generated and this value is read from ROM and held under the system variable called MARGIN. The MARGIN value is driven by the o...
by Andy Rea
Sat Nov 10, 2018 5:09 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 30854

Re: ZX81 ULA-in-a-CPLD

bit keeper is a weak feedback inside the io buffer of the xilinx chip it will retain the last known logic level on inputs without sufficiently strong pull-up / downs. i asked about the zx80 / zx81 link incase somehow the thing thinks its gone into zx80 mode. as for meaningful tests with home brew co...