I have questions about the generation of the ZX81 loading screen. Apologies for the following long winded background:
I have been writing on and off an emulator since 2010. It differs from many in that the module/class to display the video is driven only by the three state video output (1v white level, 0.5v black level, 0V sync pulse). The other emulator modules pass changes to the state along with the number of clock cycles between changes. The object is simple: Accurately simulate the computer including the hires programs. Details like the TR1 circuit and the back porch period in the display code are taken into account. The most complicated aspects seem to be achieved - see the attached Forty Niner screenshot.
However, there are two points where emulator is falling down:
1) The loading screen, where the activity is restricted to the top of the screen
2) And the prematurely terminated top video line on hires programs (see the Forty Niner screen shot)
Focusing on the loading screen issue, I have traced the problem down to sync signal being generated so long that screen code interprets it as requiring a vertical retrace after just a few rows in a video frame. The list following is an excerpt from trace of successive sync pulses during the loading of Forty Niner. Each value is the number of cycles the video output is at the sync level.
The ULA is constantly generating a horizontal retrace sync that lasts for 16 cycles (see  point 1). The majority of the entries in the above list are 11 cycles from the instructions IN and OUT (see the ROM assembly listing below). Other values (i.e 27, 19) are when the horizontal sync signal and signal created by the INs and OUTs overlap. The final long pulse results in a premature vertical retrace so all the loading video activity is restricted to the top of the screen.
Relevant ROM listing (see  for more info):
Code: Select all
L0350 0350 LD_A_BYTE 0352 IN ; TURN ON SYNC 0354 OUTA ; TURN OFF SYNC - 11 cycles 0356 RRA 0357 JR_NC 0359 RLA 035A RLA 035B JR_C L0385 035D DJNZ L0350 L0385 0385 PUSH_DE 0386 LD_E_BYTE L0388 0388 LD_B_BYTE 038A DEC_E 038B IN 038D RLA 038E BIT7 0390 LD_A_E 0391 JR_C L0388 0393 DJNZ 0395 POP 0396 JR_NZ 0398 CP_BYTE 039A JR_NC 039C CCF 039D RL_C 039F JR_NC L034E
The emulators video class expects a sync pulse of at least 15 cycles to trigger a horizontal retrace and 1235 cycles for a vertical retrace (values taken from ). Attached are a couple of screen shots, one showing the screen output if 15 cycles is used to determine the horizontal retrace. The second screenshot with activity on more rows occurs when the threshold is lowered to 11 cycles.
- What is wrong with my logic? Can anyone provide more information on the typical range of ZX81 sync values produced during loading and how the CRT display would interpret them?
 - how-the-zx81-nmi-sync-works-my-10-point ... &sk=t&sd=a
 - http://www.wearmouth.demon.co.uk/zx81.htm
 - http://nocash.emubase.de/zxdocs.htm#zx8 ... laytimings