Sinclair ZX80 / ZX81 / Z88 Forums

the ROM needs to be enabled during refresh if the IR register is pointing to an address in ROM.... during refresh the IR (well some of it, the lower A8-A0 is produced by the ULA)

Andy

As I am decoding the address bus it shouldn't be a problem because when I get a /RFSH this will activate /RD but doesn't matter because the RAM is not enabled (/CE) as long as A14 and A15 zero. For standard video with I register pointing to $1E it shouldn't be a problem. Or what do you think ?

And as A14 and A15 are low, /ROMCS is active (low). So what the heck is going on ?

Might be a timing problem ?
I enable /ROMCS with A15 and A14 low and /MREQ low.
As I see the instruction fetch cycle, /RFSH is going faster down than /MREQ during refresh.
One half cpu cycle, /RFSH going down with rising edge of T3 and /MREQ going down with the falling edge of T3.

Will try that to enable ROM either with /MREQ or /RFSH going low. Thought it could be done with /MREQ only which is active during refresh cycle, too.

Maybe I have to enable the ROM if /M1 is going down at T1 in same way ?
Here /MREQ has a delay of half cycle in comparison to /M1 same.
Is the ROM access quite slow ?

That would maybe explain why I didn't get a picture at all - the other should maybe give just wrong data /pixel on the picture but the picture should be displayed right even if ROM enable come to late during refresh - shouldn't it ?

a standard ula samples the databus for video (pattern bits) after the mreq has gone back high again, the standard ula streches the ROMCS signal...

Rather than driving /ROMCS with a logic gate, try this:-

1024MAK wrote:You could use diodes between the address lines and /ROMCS, or use logic gates driving an transistor that connects collector to +5V and emitter to the /ROMCS. Use a pull up resistor for the base to ensure the emitter voltage is a proper logic high.

1024MAK wrote:So that the ROM still works for 0000 to 1FFF, do not drive the /ROMCS when A13 and A14 and A15 are all low.

This allows the ULA to pull /ROMCS low for addresses 0000 to 1FFF.

Mark

It's still unclear for me now.
The /ROMCS addressing from me works fine when I do not connect /RD and /RFSH together via an OR gate.
This is difficult to trace with a conventional scope.

It seems that there is a conflict when RAM output data during refresh.
If I do not enable /OE during refresh all is working fine.
But the RAM can not be addressed (selected) when I register is set correct. Right ?

In a later design I will use LVL gate which can drive up to 32mA in high state (the LS gates are specified only with 1/80 = 0.4 mA).

I use a RAM with 70ns access time - so has to be fast enough.

After reading manual I found the following hint regarding the /RFSH signal.
By the way several tests while watching with my scope showed an unstable behaviour.
Sometime "K" appeared, sometimes not, sometimes "K" disappears after several seconds, sometime just stripes.

It seems that it is not stable to just use /RFSH signal without /MREQ.

The refresh signal can not be used by itself because the refresh
address is only guaranteed to be stable during MREQ time.

Found in original Zilog manual UM008005-0205.
So I maybe try not the simple "solution" with just enabling RAM output either with /RD or /RFSH than only /RD OR (/RFSH & /MREQ).

It's working now.
See "Houston we have an image" for details.

1024MAK wrote: Have a read of the instructions for a 64k RAM expansion: text file here
or scanned image files here

Mark

The scanned files have been moved here: http://k1.spdns.de/Vintage/Sinclair/80/ ... 4K/Manual/

mrtinb wrote:

1024MAK wrote: Have a read of the instructions for a 64k RAM expansion: text file here
or scanned image files here

Mark

The scanned files have been moved here: http://k1.spdns.de/Vintage/Sinclair/80/ ... 4K/Manual/

Thank you. I have edited my earlier post to update the link

Mark