ZX81 ULA-in-a-CPLD

Any discussions related to the creation of new hardware or software for the ZX80 or ZX81
McKlaud
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Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Thu Nov 08, 2018 10:56 pm

Hi Manuel,

Congratulation with your works. To be honest I stopped at the same point where you are now (issues with the NMI gen). ZX80 mode works fine, loading form tapes is good, it works fine with ZXpand+. I’ve shelved the zULA project for a while and learned a bit about CPLDS. I’ve promised myself to return to this project in early 2019. I am happy to share experience about the Alwin’s Implementation if you are up.

Cheers
Claudius
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Andy Rea
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Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Thu Nov 08, 2018 11:49 pm

Great stuff... so assuming it's not a hardware problem / bad connection, missed pull up resistor ect...

a few points,

1) intentional ( for nmi and vsync ) latches are ok ( but still better avoided) inferred latches are usually not good ( it means you don't account for all possible logic cases )

2) the hsync counter can never be stopped permanently ( only M1 low and IORQ low ) will reset ( and hold until condition is no longer met) it to a known count, 16 counts later hsync and nmi ( if nmi is enabled ) will occur.

does your memeory check out ? does it always stop working in the same way ?

Andy
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

McKlaud
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Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Fri Nov 09, 2018 12:15 am

Following Alvin's documents
1/ Hsync generation is shown below.

2/ Regarding NMI generation
Next to it 2 flip-flops that control the software-generated vertical sync, and whether the Z80 receives NMI's. A high input on "zx80_zx81" lets NMI's pass through as in a ZX81, a low input disables NMI's as in a ZX80. I have a pull-up + jumper to ground on this pin, with the ZX81 ROM it causes an annoying flicker upon each key press (= loss of screen synchronisation, as expected).
In my mind all looks fine but it can't generate /NMI correctly.
Attachments
Hsync_generator.png
Claudius
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overCLK
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Re: ZX81 ULA-in-a-CPLD

Post by overCLK » Fri Nov 09, 2018 12:22 am

McKlaud wrote:
Thu Nov 08, 2018 10:56 pm
Hi Manuel,

Congratulation with your works. To be honest I stopped at the same point where you are now (issues with the NMI gen). ZX80 mode works fine, loading form tapes is good, it works fine with ZXpand+. I’ve shelved the zULA project for a while and learned a bit about CPLDS. I’ve promised myself to return to this project in early 2019. I am happy to share experience about the Alwin’s Implementation if you are up.

Cheers
Hi Claudius. Thanks a lot. It will be really nice to share experiences and ideas to keep learning on this topic.

Cheers.

Manuel

overCLK
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Re: ZX81 ULA-in-a-CPLD

Post by overCLK » Fri Nov 09, 2018 12:42 am

Andy Rea wrote:
Thu Nov 08, 2018 11:49 pm
Great stuff... so assuming it's not a hardware problem / bad connection, missed pull up resistor ect...
Hi Andy. Thanks a lot for your feedback. Congratulations on your awesome implementation. I checked twice all the connections and even built two units to check consistent failure. :-)
Regarding pull-up resistors, I was missing the one for the US/UK line, and getting 31 NMI pulses instead of 55. But I don't think this could lead to a disabled NMI.
Andy Rea wrote:
Thu Nov 08, 2018 11:49 pm
a few points,

1) intentional ( for nmi and vsync ) latches are ok ( but still better avoided) inferred latches are usually not good ( it means you don't account for all possible logic cases )
Hmm, this is hard to follow for me so far (just starting with CPLDs and similar stuff). Do I understand correctly if I assume that you didn't follow exactly the Alwin schematic implementation? Are there inferred latches in the original implementation?
Andy Rea wrote:
Thu Nov 08, 2018 11:49 pm
2) the hsync counter can never be stopped permanently ( only M1 low and IORQ low ) will reset ( and hold until condition is no longer met) it to a known count, 16 counts later hsync and nmi ( if nmi is enabled ) will occur.
I just assumed that the NMI got disabled in the NMI service routine (just after HALT) and for whatever reason is no longer reenabled. While it is working, the timing of the NMI pulses seem ok to me.
Andy Rea wrote:
Thu Nov 08, 2018 11:49 pm
does your memeory check out ? does it always stop working in the same way ?
Not sure about this point. I have the feeling that it behaves randomly, but I'm not able to figure out whether it stops always at the same point and before or after memory check. I will have to give a closer look to the firmware code to tell.

Cheers.
Manuel
Last edited by overCLK on Fri Nov 09, 2018 12:53 am, edited 1 time in total.

overCLK
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Re: ZX81 ULA-in-a-CPLD

Post by overCLK » Fri Nov 09, 2018 12:50 am

McKlaud wrote:
Fri Nov 09, 2018 12:15 am
Following Alvin's documents
1/ Hsync generation is shown below.

2/ Regarding NMI generation
Next to it 2 flip-flops that control the software-generated vertical sync, and whether the Z80 receives NMI's. A high input on "zx80_zx81" lets NMI's pass through as in a ZX81, a low input disables NMI's as in a ZX80. I have a pull-up + jumper to ground on this pin, with the ZX81 ROM it causes an annoying flicker upon each key press (= loss of screen synchronisation, as expected).
In my mind all looks fine but it can't generate /NMI correctly.
Hi Claudius.
In my observations, NMIs are generated OK, as far as they don't get disabled. They follow IIRC the HSync signal and are controlled by the zx80_zx81 line (which I also have setup as a pull-up + jumper). I also have the same behaviour with the pin grounded: No slow video mode, and flickering like in a ZX80, what is consistent with the absence of NMIs.

Looking at the analyzer output I don't see any further IOREQ/WR/A0/A1 combination to re-enable the NMI generation. The next thing I want to check is whether there is some condition in the firmware code that could lead to this situation. But at least the analyzer output is consistent with the fact that the NMI is disabled.
Cheers.

Manuel

McKlaud
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Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Fri Nov 09, 2018 1:08 am

Bear in mind that the main difference between ZX80 and ZX81 is this NMI generator. Disabling it via pulling ZX80_ZX81 line down, you block the NAND gate regardless of status of Hsync and NMI_on lines.

The NMI_on is latched and started by /IORQ, /WR & A0 being low (any value sent to port 0xFE) and cleared by /IORQ, /WR & A1 being zero (by any value sent to port 0xFD). That is correct operation.
Attachments
NMI.png
Claudius
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Andy Rea
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Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Fri Nov 09, 2018 5:31 pm

so 2 of you following the same schematic are having the same issue with NMI generation....

there must be something weird going on...
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

overCLK
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Re: ZX81 ULA-in-a-CPLD

Post by overCLK » Sat Nov 10, 2018 10:26 am

McKlaud wrote:
Fri Nov 09, 2018 1:08 am
Bear in mind that the main difference between ZX80 and ZX81 is this NMI generator. Disabling it via pulling ZX80_ZX81 line down, you block the NAND gate regardless of status of Hsync and NMI_on lines.
Yes, completely agreed. The goal is to have it working in Slow Mode (i.e.: with NMI generation running).
McKlaud wrote:
Fri Nov 09, 2018 1:08 am
The NMI_on is latched and started by /IORQ, /WR & A0 being low (any value sent to port 0xFE) and cleared by /IORQ, /WR & A1 being zero (by any value sent to port 0xFD). That is correct operation.
Yes, that's what I meant by 'enabling and disabling NMI generation'. I'm afraid I was mixing both concepts in my explanations:
- The screenshots and failure info I provided are with the zx80_zx81 line not pulled down.
- When I was talking about NMIs being disabled and not being reenabled, I meant that an OUT operation with A0 = 0 came and no further OUT operation with A1 = 0 is detected afterwards. So, the behaviour of the CPLD seems to be consistent with the observations. It's unknown to me why the OUT operation to reenable the NMI doesn't happen.

McKlaud
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Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Sat Nov 10, 2018 12:51 pm

Looking at your snapshots, the NMI generation was re-entered successfully a few times and then stopped The is something weird going on. I think the same is going on in my case.
Claudius
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