Minstrel 3, WRX, UDG and CHR$128

Any discussions related to the creation of new hardware or software for the ZX80 or ZX81
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Mustermann
Posts: 27
Joined: Sun Dec 22, 2019 12:09 pm
Location: Augsburg, Germany

Minstrel 3, WRX, UDG and CHR$128

Post by Mustermann » Sun Feb 02, 2020 3:23 pm

From the beginning Minstrel is able to run:
- Low res graphic(e.g. 3D Monster Maze, 3DMonsterMaze.p)
- Pseudo hi res graphic(e.g. Manic Miner, manic.p)
- WRX hi res graphic(e.g. Space Invaders , invaders.p)

but not
- UDG hi res graphic(e.g. Breakout, breakout.p)
- CHR$128 hi res graphic(e.g. Panic HR, panicohr.p)

I am able to confirm all of that.

Next challenge is enabling UDG and CHR$128. Challenge accepted.

Step 1 UDG:

Based on that article
viewtopic.php?t=1514
I cut CPU_A0 to CPU_A8 legs at RAM chip and connected them to ROM_A0 to ROM_A8.
I also cut CPU_A9 leg at RAM and connected it to the corresponding pin at ROM. This doesn't have any effect yet but will be necessary for CHR$128.

My expectation was:
- Low res graphics work
- Pseudo hi res graphics work
- WRX hi res graphics will no longer work
- UDG hi res graphic work
- CHR$128 hi res graphic partially work with half of the characters

Result:
- Minstrel still alive ;)
- Low res graphics work :)
- Pseudo hi res graphics work :)
- UDG hi res graphic work :D
- CHR$128 hi res graphic partially work with half of the characters :D
- WRX hi res graphic STILL WORK :o :o :o

I am happy being able to run UDG hi res graphics games now.
But I am totally confused, why WRX graphics still work.

My under standing was, that UDG is reading graphics from RAM in RFSH cycle using line counter and data from character table, same as operating system is does from ROM.

WRX is reading graphic from RAM in RFSH cycle using I and R register addressing RAM.
I do not have any clue why this may work after I connected A0-A8 RAM address lines to ROM address generator.

Is anyone able to guess why this is working?

Confused Max
Attachments
Invaders.jpg
panic.jpg
Breakout.jpg
ZX81 issue 1 near to original state
ZX81 issue 1 under construction (64k internal ram)
Minstrel 3 ZX81 clone 64k with battery backup, UDG and CHR$128 enabled

nollkolltroll
Posts: 292
Joined: Sat Sep 27, 2014 8:02 pm
Location: Stockholm, Sweden

Re: Minstrel 3, WRX, UDG and CHR$128

Post by nollkolltroll » Tue Feb 04, 2020 7:43 am

A very nice mod, with an exciting future. Will stay tuned.
/Adam

Mustermann
Posts: 27
Joined: Sun Dec 22, 2019 12:09 pm
Location: Augsburg, Germany

Re: Minstrel 3, WRX, UDG and CHR$128

Post by Mustermann » Sat Feb 15, 2020 7:22 pm

I was able to demystify the WRX miracle.
It had been an layer 8 error(located between my ears).

All of the programs I used for testing WRX

invaders.p
pacman,p
Against_The_Elements (Paul Farrow 2016) [V1-01].p

were pseudo HRG programs in actual fact.

So I searched around for real WRX programs and found

weedkill.p
hero.p

Both of them loaded, but brought only weird signs to the screen(as expected for WRX after my mod).

So my expectation is meet:
- Low res graphics work
- Pseudo hi res graphics work
- WRX hi res graphics doesl no longer work
- UDG hi res graphic work
- CHR$128 hi res graphic partially work with half of the characters

Next step on t<my list is CHR$128

After implementing another mod now I am able to run CHR$128 as well.

Tested with
3DMaze.p

When schematic is drawn, I will tell how to do that.

Max
Attachments
3DMaze.jpg
ZX81 issue 1 near to original state
ZX81 issue 1 under construction (64k internal ram)
Minstrel 3 ZX81 clone 64k with battery backup, UDG and CHR$128 enabled

Mustermann
Posts: 27
Joined: Sun Dec 22, 2019 12:09 pm
Location: Augsburg, Germany

Re: Minstrel 3, WRX, UDG and CHR$128

Post by Mustermann » Sat Feb 22, 2020 8:25 am

Step 2 CHR$128:

In the first step I already implemented UDG capability into MInstrel 3.

So what is the difference between UDG and CHR$128?

Both are using customized character-sets located in RAM. Within RFSH cycle both are building pattern address based on line counter and character in DFILE. UDG is using one characterset as ROM does, CHR$128 is using two of them.

UDG is using A0-A8 to do so. CHR$128 is using A0-A9 to be able to address two character-sets.

The central question is; How to generate A9 in RFSH cycle?

I found information about that in an article about TK85 of Kelly Murta
http://zx81.eu5.org/chr128.html
and the build instructions of ZX97lite of WIlf RIgter
http://www.user.dccnet.com/wrigter/inde ... 97lite.htm

Both of them propose to make A9 out of INVERT bit of the Character.
ZX81 is keeping characters in DFILE. Bit 0-5 are naming the character, Bit 6 is ending character generation. Bit 7 say if the character is inverted(white on black) or normal(black on white)

Both articles are telling that lowest bit of I Register can be used to distinguish between CHR$128 and standard mode.
This bit is not used and set to 0 in standard mode but can be set to 1 to enable CHR$128 mode.
This bit is visible on A8 line in RFSH cycle. It is masked by bit 5 of the character so using standard hardware it is unused.

A8 is accessible at CPU. In the original ZX81 INVERT is hidden inside of the ULA. The Minstrel 3 design make this information accessible as the TK85 and ZX9zlite does.
INVERT can be found at pin 12 of IC15 at Minstrel 3

Kelly proposed to use NOT(A8 AND INVERT) for A9 in RFSH cycle.
WIlf propose to use A8 AND INVERT for A9 in RFSH cycle.

I tested both of them and A8 AND INVERT worked for me.
But I wasn't complete satisfied about that.
A8 AND INVERT was ok for all CHR$128 programs. In case of not using CHR$128(A8=0) the A9 line will always be 0. This work for many programs but not all. Especially when using a copy of ROM in RAM CHR$128 is disabled, so A8=0 and A9=0 as well. This does not match the position of character pattern in ROM($1E00 that has Bit 9=1)

So I propose to use A9 in standard mode and INVERT in CHR$128 mode. This can be done by (A9 AND (NOT A8)) OR (INVERT AND A8)

I implemented that with one additional 74 HC257(IC_N1) soldered on the back of IC14 to create A9 for RAM chip. I cut the A9 leg at RAM and connected it to the output, RFSH to select A9 to the input used at any non RFSH cycle and (A9 AND (NOT A8)) OR (INVERT AND A8) at the second input.

To implement (A9 AND (NOT A8)) OR (INVERT AND A8) I chose an 74HC 251(IC_N2). In case A8 is low, selector(IC_N1) is connected to A9. In case of A8 is high selector(IC_N1) is connected to INVERT.

This work for me.

So now I am able to run UDG and CHR$128 programs :D on Minstrel 3 but not WRX programs :|

Happy Max
Attachments
Panic_1.jpg
3DMaze.jpg
CHR$128.jpg
ZX81 issue 1 near to original state
ZX81 issue 1 under construction (64k internal ram)
Minstrel 3 ZX81 clone 64k with battery backup, UDG and CHR$128 enabled

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