ZX81 ULA-in-a-CPLD

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Andy Rea
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Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Mon Mar 19, 2018 1:39 pm

siggi wrote:
Mon Mar 19, 2018 12:34 pm
Andy Rea wrote:
Mon Mar 19, 2018 1:14 am
the old way the force nop started at the middle ( falling edge ) of T2 however my new way, the RAMcs get de-asserted at this time but the forced nop does not start until another 1/4 cycle ( or half a 6.5mhz cycle ) The Zilog Z80a needs a 35na setup time before the rising edge of T3 when the data bus is sampled, we have about 79-35 = 44ns for the CPLD to pull the lines low and stabilize.
Hi Andy
did you also test that with additional capacitive load on the databus?
My Zeddies can drive up to 4 external cards (I/O mapped) at a small backplane connected to the edge connector. That works fine, only the /clock-signal is arriving bad at some external boards.

Siggi

PS: Maybe some complex external cards, which "listen" on the bus to the Z80 actions (like Chroma81 or ZxBlast) could also get confused by a new timing ...

PS/2: and some "switching noise" is not bad. So I can hear in the radio, that my web server is still running :mrgreen:
Hi Siggi,

I was testing with udg4zxpand and zxpand+ I can put some extra capacitors on the data bus for testing purposes. What amount of extra capacitance do you think would be appropriate?

Yes I didn't really think about external add on cards that may also be trying to sample the data bus. Maybe I'll put back the ramcs and just go with the shorter force mop. And see what happens.

Regards Andy
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

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siggi
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Re: ZX81 ULA-in-a-CPLD

Post by siggi » Mon Mar 19, 2018 2:40 pm

Andy Rea wrote:
Mon Mar 19, 2018 1:39 pm
siggi wrote:
Mon Mar 19, 2018 12:34 pm
Andy Rea wrote:
Mon Mar 19, 2018 1:14 am
the old way the force nop started at the middle ( falling edge ) of T2 however my new way, the RAMcs get de-asserted at this time but the forced nop does not start until another 1/4 cycle ( or half a 6.5mhz cycle ) The Zilog Z80a needs a 35na setup time before the rising edge of T3 when the data bus is sampled, we have about 79-35 = 44ns for the CPLD to pull the lines low and stabilize.
Hi Andy
did you also test that with additional capacitive load on the databus?
My Zeddies can drive up to 4 external cards (I/O mapped) at a small backplane connected to the edge connector. That works fine, only the /clock-signal is arriving bad at some external boards.

Siggi

PS: Maybe some complex external cards, which "listen" on the bus to the Z80 actions (like Chroma81 or ZxBlast) could also get confused by a new timing ...

PS/2: and some "switching noise" is not bad. So I can hear in the radio, that my web server is still running :mrgreen:
Hi Siggi,

I was testing with udg4zxpand and zxpand+ I can put some extra capacitors on the data bus for testing purposes. What amount of extra capacitance do you think would be appropriate?

Hmm, good question.
Here at page 82

http://datasheets.chipdb.org/Mostek/3880.pdf

they use 50 pF data bus load for the Z80:
DATA-Bus-Load-Z80.jpg
I think, the ULA should be able to drive the same load, if the timing requirements are similar to those of the Z80.

Siggi
My ZX81 web-server: online since 2007
http://zx81-siggi.endoftheinternet.org/index.html

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Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Mon Mar 19, 2018 3:09 pm

I all Zeddys that I've got the NEC Z80 clone is sitting. The uPD780C datasheet is referring to:
  • Address lines 50pF
  • Data lines 200pF
200pF load looks like an extreme for me.
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D780C-1_CL.jpg
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Andy Rea
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Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Mon Mar 19, 2018 3:37 pm

I've been thinking about this... And well I have come to the conclusion that it's all a bit academic... The ula is connected directly to the CPU data bus.. there is a 470 ohm resistor between it and the external data bus... That external bus can be held high by whatever is connected and the ula should still be able to drive a low input to the CPU.... So capacitance is not really relavent at the force nop point in time... Obviously to much capacitance can and will affect normal operation...

@siggi i wonder if it's possible to have a back plane that has a bi directional buffer for the data bus?

Regards Andy
Last edited by Andy Rea on Mon Mar 19, 2018 6:26 pm, edited 1 time in total.
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siggi
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Re: ZX81 ULA-in-a-CPLD

Post by siggi » Mon Mar 19, 2018 4:06 pm

Andy Rea wrote:
Mon Mar 19, 2018 3:37 pm

@siggi i wonder if it's possible to have a back plane that has a bi directional buffer for the data bus?
The databus driver of ZX96 (old project) an Torsten's remake have a bidirectional databus driver (74LS245 or similar). But they need an enable signal (/BUSCS) generated by the card behind der bus driver card. See here (the bus driver card is in the center of the picture)

http://forum.tlienhard.com/phpBB3/viewt ... 275#p28817

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Re: ZX81 ULA-in-a-CPLD

Post by PokeMon » Mon Mar 19, 2018 11:00 pm

Andy Rea wrote:
Mon Mar 19, 2018 1:14 am
Well i have had a positive day, drawing timing diagrams and then working out timings based on actual chip specifications, i have also reduced the switching noise during a forced nop somewhat..

the old way the force nop started at the middle ( falling edge ) of T2 however my new way, the RAMcs get de-asserted at this time but the forced nop does not start until another 1/4 cycle ( or half a 6.5mhz cycle ) The Zilog Z80a needs a 35na setup time before the rising edge of T3 when the data bus is sampled, we have about 79-35 = 44ns for the CPLD to pull the lines low and stabilize. i have tested this new approach with zilog 1984 vintage CPU ( probably nmos i guess, a nire modern 2005 vintage zilog Cmos variety, an SGS thimson Z80a of unknown but guessing 80's and finally an NEC D780C of 1982 vintage, all appear to work fine with this forced nop scheme.

Regards Andy
Well - what I can say to the behavior of the real ULA (when implementing the M1NOT external feature for ZXblast over the bus):

As soon as the databus is latched from the ULA (char value) the databus is just overdriven with open collector drivers from D0-D7 except D6. When D6 is low and /M1 and A15=1 and desirable A14=1 the open collectors draw the data bus down (D6 doesn't need it as it is low in this case) as long as D6 is low and /M1 and address bus conditions are met.

Maybe you can implement it as simple as it was done by Sinclair/Ferranti. It is definitely not based on any clock period except that the char value has to be catched first from the ULA.

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Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Wed Mar 21, 2018 12:54 pm

Hi Karl,

At what point is M1 signal forced to high by external hardware? Knowing this would enable me to hopefully ensure compatibility. Better still are any zxblast ( preferably complete assembly ) going to be for sale?

Regards Andy
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

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PokeMon
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Re: ZX81 ULA-in-a-CPLD

Post by PokeMon » Wed Mar 21, 2018 9:05 pm

I will send you a kit. I will take a closer look at the software before getting in sale with these (have about 50 or 60 boards here).

Thinking about it - you shouldn't take much care if and when M1 is removed if you realize it not with a latch (which is not necessary at all).
But I will take a look for you. 8-)

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Re: ZX81 ULA-in-a-CPLD

Post by PokeMon » Wed Mar 21, 2018 9:38 pm

In fact I do not overdrive /M1 but A15. Changed that approach maybe because /M1 has usually more load than A15.

Well A15 is forced low temporarily with falling edge of T2 (see Z80 M1 timing diagram) and released when /MREQ goes high. It is realized with a 5 input and gate and the result of the gate is clocked into a flipflop with rising edge of clock on the ZXblast (which is falling edge while the connector clock is inverted) and the flipflop is cleared whenever /MREQ goes high.

The condition is:
A15=1, no video code execution (A15/A14/M1), M1=0, /MREQ=0 and a config bit must be set (enable this feature).
So A15 is forced low for half a clock cycle plus 60-80ns (release time of /MREQ).
That's how it is implemented.

By the way - this does not work with internal RAM but this is switched off anyway. This feature works with ZXblast's RAM only. But I think this doesn't really matter. A15 is temporarily stored internally. Should work with internal flash rom as well - didn't test yet. So when drivers are located in ROM.

Bildschirmfoto 2018-03-21 um 21.29.43.png

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Andy Rea
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Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Wed Mar 21, 2018 11:00 pm

And you have this working with a genuine ULA? That means the test for a video cycle happens between falling edge of T2 and rising edge of T3... Where as I am testing for video cycle at the falling edge of T2. And this would still see A15 high.

I can alter logic to test video a little later.

Regards Andy
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

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