ZX81 ULA-in-a-CPLD

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McKlaud
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Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Wed Mar 21, 2018 11:10 pm

Very, very interesting discussion, I am reading and learning a dark magic of Zeddy from both of you. :geek: Thanks a lot gents.
Claudius
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Andy Rea
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Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Wed Mar 21, 2018 11:40 pm

Ah Claudius, I have made some small progress with reducing video noise, the following circuit is what I have now, V1 and V2 come from the cpld

Roughly V2 is sync and v1 is pixel data
Anyway into 75 ohm.load

V1 = 0 V2 = 0 output = 0
V1 = 0 V2 = 1 output = 0.3v approx it's very close
V1 = 1 V2 = 1 output = 1v approx it's also very close
Transistor Vbe is approx 0.7v

It will run into high z input monitor also because 100 ohm resistor in emmiter still provides a load , but voltage out is approx 200mv higher.

The 4.7 ohm resistor is for short circuit protection with full white video and a shorted current through the transistor is approx 100 ma 200ma and it should survive no problem.

The power is now off the 3.3v rail and is filtered with a ferrite bead and 0.1uf and 1uf caps. Although I am not even sure the ferrite has any effect of it does it is small, maybe the noise frequency is too low for this to be effective. I looked for beads with high resistance, maybe I need to look for ones active at lower frequency.
1521670970697347750157.jpg
Regards Andy
Last edited by Andy Rea on Fri Mar 23, 2018 10:10 pm, edited 1 time in total.
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

McKlaud
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Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Thu Mar 22, 2018 12:16 am

Hi Andy,

Looks interesting. I'd added and tested the ferrite bread + caps (0.1uF and 10uF) in similar fashion as you shown above, but it didn't help much in my case. I think the issue is with the noise coming to the ULA PCB from the Zeddy mainboard. It seems that the +5V and GND are the carriers. So switching to the regulated and properly filtered +3.3V supply to drive the video output might be a good idea.

On my end I struggle with the /NMI generator in the RetroTechie implementation and will spend a time with the iSim checking timings there this weekend. Fingers crossed, and hope my ULA will work in the SLOW mode finally.
Claudius
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PokeMon
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Re: ZX81 ULA-in-a-CPLD

Post by PokeMon » Thu Mar 22, 2018 9:39 am

Andy Rea wrote:
Wed Mar 21, 2018 11:00 pm
And you have this working with a genuine ULA? That means the test for a video cycle happens between falling edge of T2 and rising edge of T3... Where as I am testing for video cycle at the falling edge of T2. And this would still see A15 high.

I can alter logic to test video a little later.

Regards Andy
Yes - this works with a genuine ULA as the force-NOP logic is not clock bound. It is just open collector array which is forced when D6=0 and A15,/M1 condition is true. As soon as A15 or /M1 changes (or D6) the oc array is released. It is driven by simple logic function.

Yes - would be better to test 1/4 clock later as you have double clock in your system. It works with a real zeddy as the data bus content doesn't count for me, so access time of RAM is irrelevant. On the other hand I switch off internal RAM. :roll: But I don't need D6 for this feature.

By the way it can not handled with D6 only for me due to the simple construction. I had to force D6=1 even when D6 should be 0 for the M1NOT code execution still databus is read by CPU. This can not realized this way with D6, otherwise wrong instructions are executed later.

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PokeMon
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Re: ZX81 ULA-in-a-CPLD

Post by PokeMon » Thu Mar 22, 2018 9:44 am

McKlaud wrote:
Thu Mar 22, 2018 12:16 am
Looks interesting. I'd added and tested the ferrite bread + caps (0.1uF and 10uF) in similar fashion as you shown above, but it didn't help much in my case. I think the issue is with the noise coming to the ULA PCB from the Zeddy mainboard. It seems that the +5V and GND are the carriers. So switching to the regulated and properly filtered +3.3V supply to drive the video output might be a good idea.
That's what I do in the ZX8CCB. I create 3.6V from 5V with just two 1N4148 diodes, buffered with a 10uF SMD X7R. This is used for my output drivers (74LVC logic) and this is clean enough to have a steady white background with no stripes at all.

PS: In fact I use a SOT23-3 BAV99 double diode on the ZX8CCB.

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Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Thu Mar 22, 2018 10:06 am

In my case I create +3.3V for the CPLD from the Zeddy +5V rail using LM11117-3.3V plus 4 capacitors (100nF & low ESR 10uF) at both sides (in & out). However, for video output buffers I've decided to go for +5V which is noisy. So, it is time to change and don't use +5V rail from the Zeddy board for anything else than the LDO.
Claudius
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Andy Rea
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Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Thu Mar 22, 2018 11:03 am

This is all good stuff...

@karl very interesting doing the force nop like the zx80... I think I am going to try a new approach then, using "simple logic" to detect video condition but also only allow the actual forced nop during the quarter cycle upto the rising edge of T3 also I may only trigger a full video cycle if forced nop is actually happening on that rising edge of T3. This should allow for maximum comparably with other hardware.

@claudius, yes that is more or less what i have, except I didn't bother with the 10uf on the input side of the regulator but do have 0.1uf... I nearly always have those input and output, I have had the misfortune of regulators oscillating before 😣
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

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PokeMon
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Re: ZX81 ULA-in-a-CPLD

Post by PokeMon » Thu Mar 22, 2018 12:40 pm

McKlaud wrote:
Thu Mar 22, 2018 10:06 am
In my case I create +3.3V for the CPLD from the Zeddy +5V rail using LM11117-3.3V plus 4 capacitors (100nF & low ESR 10uF) at both sides (in & out).
As in Sinclair's philosophy I don't waste money for voltage regulators not needed. There is already a voltage regulator for 5V that's enough. All you need for the CPLD is to lower the voltage. Diodes are good for this and the BAV99 cost about 5 cent only - in larger quantities getting down more. 3.3V or 3.6V is quite irrelevant for function, just a convention.

What I think is that the 5V coming into your board are made dirty from the CPLD. I would propose to have two separate rails for logic and video power supply made from the 5V. Should give more clean background in the video.

McKlaud
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Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Thu Mar 22, 2018 1:26 pm

@karl: At the moment I have got two power rails on the PCB, one is +5V directly from the Zeddy board and the second is +3.3V rail for the CPLD. The video output of the CPLD is connected to a transistor buffer. The transistor is fed off the +5V Zeddy rail to avoid any CPLD switching noise on the +3.3V rail. Anyway this the video output noise the lowest priority item on my TO DO list.
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1024MAK
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Re: ZX81 ULA-in-a-CPLD

Post by 1024MAK » Thu Mar 22, 2018 6:24 pm

I strongly recommend a separate filtered supply for the video. If going for a 5V supply, use a RF choke / inductor from the Zeddy +5V to two filter capacitors, one a 100nF ceramic, one a 47uF or a 100uF electrolytic (low ESR type if possible) or a couple of 10uF multilayer ceramics in parallel. If you have enough voltage swing on the transistor, a 47 ohm resistor (to limit the short circuit current if the video output is shorted to 0V/GND) can be wired in series with the choke (assuming the resistance of the RF choke does not achieve the same thing).

Same arrangements if using the CPLD supply voltage, use a filter.

Or you can generate a completely separate +3.6V supply using two diodes as Karl describes. In this case, you may not need the RF choke, but the resistor and capacitors should be retained.

The power supply lines (including 0V / GND) will always be noisy in any digital computer. So ideally the 0V/GND used for the video should be a separate track between the source of the signal (the CPLD in this case) and the video output terminal. Don't connect non-video circuitry to this 0V/GND track. Or keep the distance between them as short as possible. Think star topography.

Mark

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