QuickSilva HRG graphic card emulation !

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XavSnap
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Re: QuickSilva HRG graphic card emulation !

Post by XavSnap »

Thanks Wilf !
Sorry for this question ...
But, your answer help me !

You allready answer that :
QUESTION:
WRX16 Inverse display: One of the known subtleties with emulation
of WRX16 CODE is reversing the dummy display file by setting bit 7
high to get an inverse display. Could someone explain why?

Finally, has a functional version of WRX16 Video ever been released
into the public domain for experimentation that eliminates the need
of the ghost dummy display file?

ANSWER:
Simple question which requires a signifcantly more complex answer.

For me it is an opportunity to refresh my own memory with some
details of that wonderfully versatile video system. Let me answer
then with a short summary of the original ZX81 video system:

The original ZX81 DFILE is actually a kind of low level subroutine
which is executed to generate the video display.

That may not be obvious since DFILE seems to contain display
character codes and not machine code. The secret of the ZX81 video
system hardware is the special decoding of the Dfile "opcodes" which
are executed as normal opcodes if A15 is high and bit 6 is high (ie
the newline or HALT character) but if bit 6 is low, then the actual
code is ANDed with 00 and is executed as a NOP instruction.

Although bytes with legal ( bit 6 low) character codes in the Dfile
are executed as NOPs, the character code data is not discarded.
Seven bits of the character code are latched into the ULA with 6 LSB
bits of the character code are used in conjunction with the ULA line
counter and the Z80 I register to address the actual display pixels
in a 512 byte video pattern lookup table in the ROM. All this happens
during the execution of each Character byte in Dfile.

For each horizontal video line, the result is a stream of 256 pixels
from the video shift register serial output. The pixels correspond to
the 256 bits (8x32 bytes) of video pattern data fetched from the
table in ROM.

As the video is shifted out of the ULA video shift register, it is
XOR'd with bit 7 of the each of DFILE character codes and the
corresponding 8 video pixels are inverted if bit 7 is high.

The HALT codes are executed as opcodes and the HALT state is exited
when the Z80 INT line (connected to A6) goes low. That ends the
execution of each line of 32 (or less) DFILE characters, and returns
to the main video subroutine which increments the 3 bit line counter
in the ULA (the 3 LSB address bits to the ROM lookup table) and then
jumps back to execute each line of DFile characters 8X. This process
is repeated for 24 rows of characters until the whole display file is
executed.



So far so good, now what about WRX16 video?

With few exceptions all ZX81 hires video routines use the Z80 dynamic
RAM refresh hardware to fetch the actual hires video data during each
memory refresh state at the end of each M1 opcode cycle while
executing the character codes in the Dfile.

The dummy display file of WRX16 is similarly executed during slow
mode video display for each of the 192 horizontal video lines.

Unlike the 32x24 character codes in the ZX81 Dfile, there are just 32
character code bytes of either $00 or $80, with bit 7 determining
which column of 8 pixel wide by 192 lines high hires pixels is
displayed as true or inverted video.

The execution of the dummy display file subroutine is also closely
coupled to the ZX81 video hardware, loading the video shift register
with hires display file data and loading the ULA XOR register with
bit 7 of the 32 character code bytes to invert each of 32 collums of
8 pixels wide by 192 pixels high .


The character code register and the 1 of 8 line counter in the ULA
normally used to address the video pattern table in ROM are not used
in WRX16 hires . Since the hires video display data is not located in
ROM, so it is not accessable to the ULA address lines connected to A0-
A8 and must be addressed some other way.

The video display data is loaded into the video shift register
during refresh. The I and R registers are loaded on the Z80 A0-A15
address lines during refresh. All we have to do is use the I and R
registers to address the hires video display data.

There are several variations of the WRX16 video routine but they all
share the same basic method.

During memory refresh, the Interrupt Register and the Refresh
Register are used as a 16 bit address pointer. The R register
autoincrements the 7 least significant bits, so bit 7 of the R
register does not autoincrement. The I register is loaded with the
MSB of the address to the start of the next hires video line. Next a
CALL is made to the dummy display file echo above 32K (A15 set high)

The dummy display file "subroutine" begins with LD R,A (bit 6
high). The R resister is loaded with the LSB which together with
the MSB in the I register forms the address to the start of 32 hires
data bytes.

Next in the dummy display file comes a group of 32 NOP opcodes (bit 6
low) and bit 7 set high or low. As these 32 opcodes are AND'd with 00
by the ULA and are executed as NOPs, the R register auto increments
and the next hires data byte is accessed. The last byte in dummy
display file is a RET opcode which returns control to the calling
hires display program.



I believe the above is correct if memory serves me right and
hopefully answers your questions about bit 7 and the necessity of the
dummy display file which is after all really a display subroutine.

For more details also check the ZX81 video tutorial ( I know I should
have but where did I put the darn thing? Anyone?) which includes
anotated code for several hires programs including WRX16.

If there is some interest I may do a revison of the tutorial and add
some proper graphic diagrams.

Who knows, perhaps yet another version of ZX hires may be discovered
that is even weirder and does away with the DFILE concept altogether.

regards
wilf

I understand ... but ...
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Xavier ...on the Facebook groupe : "Zx81 France"(fr)
User avatar
XavSnap
Posts: 1940
Joined: Sat May 10, 2008 4:23 pm
Location: 'Zx81 France' Fb group.

Re: QuickSilva HRG graphic card emulation !

Post by XavSnap »

Hi,

My QuickSilva HRG page is ready...
http://zx81.ordi5.free.fr/qshrg
(It's a frensh page !!!)

But, there's beautyfull pictures...
arrrghh !!!
Xavier ...on the Facebook groupe : "Zx81 France"(fr)
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