Sinclair ZX80 / ZX81 / Z88 Forums

Could it be that the ULA of the ZX81 generates HSYNCs independent of INTs such as the design of the ZX97 (Wilf Rigter's pages)? And that the driver does not work on a ZX80 with a ZX81 ROM and NMI generator (if Chroma supports the ZX80)?

Thats a cool video driver, i have tinkered a little with Sponzy on the 20Mhz Zeddy, indeed it runs at a very respectable speed

@pokemon the hsync generator is free running, you cannot stop it on a real ZX81 ( unless you generate int ack's every 16 cycles or less, but thats another story )

Regards Andy

Andy Rea wrote:@pokemon the hsync generator is free running, you cannot stop it on a real ZX81 ( unless you generate int ack's every 16 cycles or less, but thats another story )

This is new for me and a significant difference to the ZX80 (with NMI generator circuit).
I think even the NMI generator from Grant Searle does not produce a steady hsync.
So this would mean, that some HRG programs may not run depending on how they are realized.
Am I right ?

And how is synchronisation done ? Just waiting for next NMI in the program ? Or any other mechanism ?

PokeMon wrote: I think even the NMI generator from Grant Searle does not produce a steady hsync.

Okay - it does give a steady sync, as I checked.
http://searle.hostei.com/grant/zx80/zx80nmi.html

So this is then a HRG problem of the old ZX80CORE. Will solve it on the new version.

>@pokemon the hsync generator is free running, you cannot stop it on a real ZX81 ( unless you generate int ack's every 16 cycles or less, but thats another story )

Probably it is the reason for the garbled picture I got with my crap attempt. I mention it just to be precise, since I vaguely referred to the R register before; I stop developing on it because of the lack of colours where the only benefit of such timing was the possibility to loop between many text line buffers.

Andy Rea wrote: ( unless you generate int ack's every 16 cycles or less, but thats another story )

Is the INT ACK used for synchronizing the hsync generator ?

Exactly, the int ack resets the hsync counter and will hold it until the int ack releases, the hsync pulse then starts 16 clock cycles later

Regards Andy

The delay between int ack and the hsync is why aszimic & other display drivers can have scan lines more than 207 cycles long, towards the end of the scan line we are expecting an int to occur some cycles before the hsync ia due, however if the int is delayed by say 4 cycles the hsync counter will reset and the hsync will also be delayed.

Regards andy

Many thanks.

With the Olofsen contribution, z88dk is now Chroma-81 compatible
All the improvements will be online soon.

zcc +zx81 -subtype=chroma -clib=chroma -create-app -Dspritesize=8 -DBANNERS -DSPECTRUM -O3 wall.c
...powerful, isn't it ?

.. would you mind to take a picture of the real hardware in action ?