Z80 special reset

[PokeMon]

Does anybody know about the special reset of the Z80 processor ?
This has been patented from ZILOG but never really documented except in the patent script.
I think ZILOG developed some ICE (in circuit emulators) for debug purposes of Z80 systems.

It works quite simple and this reset pulse has to be short and exactly during rising edge of T2 only and does only a partial reset of the program counter to address 0. That's maybe the reason why the reset pulse is described to stay for minimum 3 T states in the datasheet to avoid an accidently partial reset. Curious feature, isn't it ? Found this document yesterday on the web.

http://www.primrosebank.net/computers/z ... _reset.htm

[Andy Rea]

A most interesting read, thanks

[RetroTechie]

Indeed! (read it earlier this year). Not of much practical use I think, but a local copy did make it into my Z80 documentation...

That's maybe the reason why the reset pulse is described to stay for minimum 3 T states in the datasheet to avoid an accidently partial reset.

Usually with a complex mix of sequential & combinatorial logic like a CPU, a reset needs a number of clock pulses to 'ripple through' such that all affected registers / flip-flops are returned to a defined state.

3 T states is a pretty low number for that, compared to some other CPU's / SoC's. Which you could see as an indicator of the relative 'simplicity' of a Z80. Of course most systems will use a reset pulse that is waaaaayyyyy longer than a few cpu cycles.

[PokeMon]

3 T states is a pretty low number for that, compared to some other CPU's / SoC's. Which you could see as an indicator of the relative 'simplicity' of a Z80. Of course most systems will use a reset pulse that is waaaaayyyyy longer than a few cpu cycles.

That's the reason why the Z80 functions properly with simple R/C combination for a reset connected to power. This could result in several fast resets one after eachother if the reset input does not have a schmitt trigger characteristic which the Z80 doesn't have, I think. But in fact there is really no technical reason why the reset pulse has to be quite long - okay you should avoid spikes on the reset for sure. But in the same way as the CPU "stores" a very short NMI pulse to be executed later at the end of the current instruction it would be possible to the same with a short reset pulse, keep it inside the CPU as long as it needs and reset the internal flipflop when reset is completed. As I understood the documents, the reset pulse for minimum 3T states is necessary only to avoid a short reset or distinct it from a regular reset with when the reset occures at a wrong point (during T1 of M1 for example).

When I think about that modern CPU's have millions or even billions of transistors it wouldn't be hard to realise a reset latch inside.

[1024MAK]

A little more here

Mark

[PokeMon]

Thanks, this one was an interesting read, too.

http://www.z80.info/zip/ZilogProductSpe ... 29-143.pdf