Hi all,
I asked the following on the ZX81 Owners Facebook group but I suspect for techy questions that I’m better asking here. Sorry for the repetition for those of you who are members in both.
How many cycles are there relative to the end of an OUT instruction until the ZX81 ends the vertical video sync signal? Before all the 11 instruction cycles complete? Exactly when the instruction finishes? A delay of X cycles?
From my own emulation experiments I think there may be a 1 cycle delay. Obviously the the ULA is continuously generating horizontal sync pulses independently. For the purposes of this question assume I’m asking at a point when there is no overlap.
Thanks,
Kevin
OUT & vertical sync timing
Re: OUT & vertical sync timing
Perhaps someone at the software or development subforum may help.
I saw you at the Facebook group but I haven't much experience in machine code..
I saw you at the Facebook group but I haven't much experience in machine code..
Ernesto
ZX80 USA, ZX81UK, ZX Spectrum, ZX Spectrum+, ZX Spectrum 128+ UK, ZX Spectrum +2/A, Sinclair QL, CZ1000, CZ1500, CZ2000, CZ1000Plus, CZ1500Plus, CZ Spectrum, CZ Spectrum Plus, TK83, TK85, TK90X, TK95. TS2068. And more to come
ZX80 USA, ZX81UK, ZX Spectrum, ZX Spectrum+, ZX Spectrum 128+ UK, ZX Spectrum +2/A, Sinclair QL, CZ1000, CZ1500, CZ2000, CZ1000Plus, CZ1500Plus, CZ Spectrum, CZ Spectrum Plus, TK83, TK85, TK90X, TK95. TS2068. And more to come
Re: OUT & vertical sync timing
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Probably would be more likely to get an answer. I guess I was hoping for more empirical based responses from this channel.
Re: OUT & vertical sync timing
I think few people know, and the ones who knows might be on vacation.
I don't ignore the post. I just don't know the answer.
I don't ignore the post. I just don't know the answer.
Re: OUT & vertical sync timing
Would this be helpful: http://searle.x10host.com/zx80/zx80nmi.html
Re: OUT & vertical sync timing
Paul Farrow kindly sent me a detailed explanation after I emailed him separately. To save anyone else going to the trouble of answering, it’s about 3 cycles before the end of the OUT instruction. Part way into the port write machine cycle of the instruction.
I’ll leave Paul with the honours of explaining when/if he gets get time.
I’ll leave Paul with the honours of explaining when/if he gets get time.