This weekends projects

Discussions about Sinclair ZX80 and ZX81 Hardware
mcarlson_sb
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Re: This weekends projects

Post by mcarlson_sb »

Mystery Solved
It was switching noise.

:oops: :oops: :oops:
I hadn't added the bypass caps to the 74xx chips
:oops: :oops: :oops:

Lesson learned.
Never underestimate the power of the bypass cap across Vcc & GND to clean up switching noise.

Ignore them at your own peril and frustration.

BTW:
The hint was that moving C13 to smooth the signal going into IC6 p1&19 worked.
For that to make a difference it had to be a very short blip. Like, say, noise on the line. :roll:

Positive:
I learn so much more when I make mistakes.
I now know how pretty much every piece of this works.

Cheers,
Matthew
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XavSnap
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Re: This weekends projects

Post by XavSnap »

Another example in Micro&Robot #7 (Amstrad Centronics port):
SPO_B.JPG
https://www.abandonware-magazines.org/a ... &album=oui
Xavier
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1024MAK
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Re: This weekends projects

Post by 1024MAK »

Look at the truth tables rather than the diagrams in the datasheets.

For the 74xx240, both /G inputs need to be logic low to enable the outputs. When logic high, the outputs are in the high impedance / tri-state mode.

This design, along with rather a lot of 1980s expansion designs does not appear to take into account the fact that a standard ZX81 has active memory at ALL addresses (due to incomplete address decoding). So when the Z80 tries reading from the address that the 74LS240 is mapped to (0x4021, 16417 dec), there will be a databus conflict with the RAM memory chip. Which is not good.

In a standard ZX81, the ROM chip appears in the Z80 memory area FOUR times. And the 1k byte RAM chip appears in the Z80 memory area 32 times. If a 16k byte RAM pack is in use, or an internal 16k byte upgrade is used, then the 16k of RAM appears in the Z80 memory area TWO times. See this topic ;)

Mark
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1024MAK
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Re: This weekends projects

Post by 1024MAK »

So taking the points I talked about (sorry!) above into account, here is a revised design.
This version is mapped into the echo of the ROM between 0x2000 and 0x3FFF, the actual address being 0x2021 or 8225 decimal.
A transistor is included to disable the ROM chip when reading the status from the 74LS240 buffer chip. The status ("standby") signal now going to data bit 0. Note that the 74LS240 inverts the input signals. As this is now in the ROM area below the RAM area, the RAM check performed at power up by the ROM code won't affect the speech chip. I also took the opportunity to include the Z80 /MREQ signal so that it's not affected by I/O port operations.
TalkBack_SPO256al2_modified by 1024MAK.png
Mark
mcarlson_sb
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Re: This weekends projects

Post by mcarlson_sb »

:shock: :) :) :) :) :) :)

You Mark = :ugeek:
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1024MAK
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Re: This weekends projects

Post by 1024MAK »

Well, before you cast me in bronze and stick me on a plinth, do try it first, just in case I’ve dropped the ball somewhere...

Mark
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XavSnap
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Re: This weekends projects

Post by XavSnap »

Hi,
I can't find the BUS expender in previous issus…
Is there any buffers/BUS amplifier/power supply in this ghost kit ? to explain this miscelencious data/address synchro...
Xavier
mcarlson_sb
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Re: This weekends projects

Post by mcarlson_sb »

I received my boards

Now I just need to solve an annoying display problem before I can try them out :(
20200824_160610.jpg
20200824_160957.jpg
And a little MtM adapter because it seemed usedful
20200824_161152.jpg
mcarlson_sb
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Location: San Francisco

Re: This weekends projects

Post by mcarlson_sb »

Process pics:
Socketed
Socketed
20200828_222538.jpg
Missed a GND trace :oops: but it was an easy fix
20200828_222635.jpg
Complete
20200828_222701.jpg
Looking forward to testing it once I get my RAM issue figured out

Cheers,
Matthew
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1024MAK
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Re: This weekends projects

Post by 1024MAK »

It’s not proper without at least one bodge wire... :)

Looking good 8-)

Mark
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