Sinclair ZX80 / ZX81 / Z88 Forums

I just finished repairing, restoring, and video-modding a ZX81 that I got off eBay. Now the only thing left is probably attempting to repair that 16kB RAM pack that came with it, because when I plug it in, either nothing or just stripes happen, even after cleaning the contacts.

Anyway, while doing research for that, I noticed multiple mentions that the onboard RAM is deactivated when using a RAM pack. (This would also further provide opportunity for a broken RAM pack makes the ZX81 not work at all.)

But what I could not find out is how it's doing that? I looked at two versions of the schematic, one low res scanned one and an apparently retraced high res one, and I don't see a mechanism. I imagine it would be on the RAM CS line, but I don't see any gates or anything similar on that. The edge connector is just a separate, floating component on those schematics, but its markings (D0-D7) indicate that it's just directly connected to the data lines as well.

While I was typing this I actually had another idea: Is the edge connector maybe connected on the other side of the 470ohm resistors, i.e. before them closer to ULA and Z80? Is that how it works?

Hello and welcome

In the 16k RAM pack, it’s a straight connection between +5V and /RAMCS’ (edge connector pin 2A). On the ZX81/TS1000 board, this is on the SRAM side of resistor R2, hence overrides the ULA /RAMCS signal on IC1 pin 12 but without damaging the ULA output pin circuitry.

Mark

There is a Sinclair 3K expansion originally built for the ZX80 that doesn't disable the internal memory.
That results in 4 K in total. So: not every rampack disables internal RAM. Also, the internal ram could be activated elsewhere. There are memotech extensions that use the internal RAM e.g. for patching the ROM.

Thank you for the warm welcome!

Mark: I think I understand. So the slot RAMCS' is effectively between ULA and R2? Is that what the apostrophes mean, which "half" (which side of the resistor) the lines are on? If it's a straight connection to 5V on the 16k pack, that means it cannot snoop RAMCS' though. So is it purely looking at the address lines to determine RAM access?

Paul: Ah, that makes sense. Clever to essentially map the internal RAM somewhere else.

anyfoo wrote: ↑Sat Jun 05, 2021 10:00 pm I think I understand. So the slot RAMCS' is effectively between ULA and R2? Is that what the apostrophes mean, which "half" (which side of the resistor) the lines are on? If it's a straight connection to 5V on the 16k pack, that means it cannot snoop RAMCS' though. So is it purely looking at the address lines to determine RAM access?

No, not quite. The ‘slot’ or edge-connector pin is in parallel with the SRAM chip select pin. Between these and the ULA output pin is the resistor. The apostrophe means that this signal is AFTER a resistor, which in turn is AFTER the output pin.

Have a look at the copy of the schematic that’s in this post (ignore the French video/TV circuitry).
The 16K RAM packs have their own address decoding, they don’t use the /RAMCS’ signal for any of their control circuitry themselves. As I said above, inside a 16K RAM pack, the /RAMCS’ signal is connected directly the the +5V line. The point of this is to hold the chip select line high (disabled) for the internal RAM chip inside the computer.

Mark

Ah, thanks a lot, that version of the schematic seems to be the same as the one I had, but with little boxes added where the edge connector pins branch off. That makes things much clearer!

And now from a quick look at the 16k RAM pack schematics, which does not use /RAMCS' except to override it, it seems like the outputs of the eight 4116 RAM chips are enabled only based on address line A14 and /MREQ and /RD or /WR. I think that makes sense to me now, also how the RAM pack strobes row and column into the 4116s by way of the Z80 putting the address onto the bus one clock cycle before /MREQ and /RD or /WR already.

If you look at the topic I linked to earlier (here’s another link), RAM address decoding is discussed.

In most low cost designs, /RAS for the DRAM chips is derived from a very slightly delayed /MREQ signal.
Then after a further delay, the multiplexer control changes state, putting the remaining part of the address to the DRAM. Then after another delay, /CAS strobes this address in.

Mark

That table is a good reference. Internal RAM access was easier to understand even with the old schematic, which already shows the full signal path (well, together with knowing where RAM and ROM are shadowed to determine that the ULA really only looks at A14).

I think I now have everything to make a serious repair attempt of the 16k RAM pack, but I will wait until the logic analyzer add-on for my scope arrives to make it a bit easier. So thanks again!

I'm not sure yet what I will do when it turns out that one or more of the 4116 are broken (which does not seem unlikely at all). I will probably just source them from eBay (seems possible), and fake it with a 5V tolerant micro, or worst case an FPGA with a few transistors or a level changer, until the chips arrive. I do have some other DRAM chips lying around that I could probably also rig into something temporary...