As the the title suggests really.
I've have often wondered how the R register served two masters. If it is used for video purposes then what is the mechanism for refreshing memory contents, or is some other means used?
If the R reg is used for video, how does it find time to refresh memory?
Re: If the R reg is used for video, how does it find time to refresh memory?
AFAIK Memotech (and Sinclair?) ram packs have their own refresh counter. And other ram packs often use static ram, which does not need refresh.
Futhermore any usual ram access also does a refresh of the accessed ram columns.
Futhermore any usual ram access also does a refresh of the accessed ram columns.
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Re: If the R reg is used for video, how does it find time to refresh memory?
To refresh DRAM, the DRAM needs each row (in a 16k bit DRAM chip there are 128 rows) to be accessed at least (according to the manufacturers datasheets) every 2ms. It does not matter if this is a write, a read or a refresh cycle. When a read or a write is performed, a DRAM has to perform a refresh cycle for that row anyway, due to the design.
The Z80 increments the refresh (R) register as normal in a ZX81. Except that at certain points the ROM or other video display routine loads the R register with a different value. So the complete binary count (of the lowest seven bits) does not follow the full sequence from 0 to 127.
So if the DRAM were to only be refreshed by the Z80 refresh cycles, some rows in the DRAM would forget their contents. Hence the first generation of Sinclair 16K RAM packs include a full counter to provide the full 0 to 127 count for the refresh cycle. The later version that uses a ULA does not include a full counter and instead only provides some counter binary digits, relying on the other binary digits to come from the Z80. This is detailed in another topic on here.
Other manufacturers either do similar to the first generation of Sinclair 16K RAM packs and include a full counter. Or don’t include ANY counters for the refresh. So how does that work?
Well, as it turns out, the manufacturers stated refresh interval is rather conservative, and some DRAM chips can retain their contents for significantly longer than 2ms. When combined with the Z80’s partial refresh (due to the way that the video system works) and the normal running of a program, enough accesses are performed such that there is sufficient refresh so that the DRAM does not forget it’s contents.
I have not tried, but if a machine code program was to enter a tight loop in certain circumstances, it’s possible that some parts of DRAM may forget their contents.
Mark
The Z80 increments the refresh (R) register as normal in a ZX81. Except that at certain points the ROM or other video display routine loads the R register with a different value. So the complete binary count (of the lowest seven bits) does not follow the full sequence from 0 to 127.
So if the DRAM were to only be refreshed by the Z80 refresh cycles, some rows in the DRAM would forget their contents. Hence the first generation of Sinclair 16K RAM packs include a full counter to provide the full 0 to 127 count for the refresh cycle. The later version that uses a ULA does not include a full counter and instead only provides some counter binary digits, relying on the other binary digits to come from the Z80. This is detailed in another topic on here.
Other manufacturers either do similar to the first generation of Sinclair 16K RAM packs and include a full counter. Or don’t include ANY counters for the refresh. So how does that work?
Well, as it turns out, the manufacturers stated refresh interval is rather conservative, and some DRAM chips can retain their contents for significantly longer than 2ms. When combined with the Z80’s partial refresh (due to the way that the video system works) and the normal running of a program, enough accesses are performed such that there is sufficient refresh so that the DRAM does not forget it’s contents.
I have not tried, but if a machine code program was to enter a tight loop in certain circumstances, it’s possible that some parts of DRAM may forget their contents.
Mark
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ZX81 Chip Pin-outs
ZX81 Video Transistor Buffer Amp
Standby alert
There are four lights!
Step up to red alert. Sir, are you absolutely sure? It does mean changing the bulb
Looking forward to summer later in the year.
Re: If the R reg is used for video, how does it find time to refresh memory?
Thanks Siggi for prompt response and thank you Mark for filling in the fine detail, succinct and to the point as always.