Simple 8-16K RAM Mod Question

[Slipstreem]

Hi guys. I'm new here and haven't had a serious dabble with a ZX81 in terms of the hardware despite being an early adopter with one in kit form back in 1981, so please be gentle with me.

That machine was sold to fund a 48K Speccy a year later, but the bug bit me again a few weeks ago, so I now have an almost mint condition Issue 1 Zeddy picked up on eBay for ~£12 delivered sitting in front of me just begging to be modified.

What I'd like to achieve is an 8KB chunk of RAM situated at 8-16KB with the lowest component count possible. I stumbled across THIS schematic (and I just so happen to have a CDM6264 sitting here), but I'm struggling to see why the three NAND gates have to be there. What would happen if I connected everything else as shown but eliminated the three gates and connected A13 to /ROMCS on the ROM? Wouldn't it give me the original ROM from 0-8KB only instead of shadowed at 8-16KB, and the 8KB of RAM from 8-16KB?

It's roastingly hot here, so answers on an ice lolly please.

[RWAP]

Now why would you want to do this, when you can have ZXpand ?

[Slipstreem]

Because I don't have the cash to spare right now, but I do have a soldering iron, and I'm not afraid to use it.

[Prime]

I stumbled across THIS schematic (and I just so happen to have a CDM6264 sitting here), but I'm struggling to see why the three NAND gates have to be there. What would happen if I connected everything else as shown but eliminated the three gates and connected A13 to /ROMCS on the ROM? Wouldn't it give me the original ROM from 0-8KB only instead of shadowed at 8-16KB, and the 8KB of RAM from 8-16KB?

I'll answer your question rather than trying to sell you something..........

Yeah but it would enable the rom whenever A13 was low not just in the 0..8K region, but also in 16K..24K etc which is not what you want.

Cheers.

Phill.

[Slipstreem]

Ah. OK, thanks. I was assuming that A13 would always be high for all addresses above 8K (D'oh!). I have a 74HCT00 knocking around somewhere, so no worries.

[Andy Rea]

OOooeee looky here....

thats one of the first mods i did to my zeddy long long time ago, because it shares the ROM's address lines you can use it for CHR$ maps but not normal HI-res, i did write a modified version of the hi-res driver based on Wilf's WRX driver.

probably telling you to suck eggs, but remeber you need power and an additional 0.1uF cap across the supply near the ram chip wont hurt either.

Andy

[Slipstreem]

Aha! So am I right in thinking that constructing the same circuit but picking up the address lines at the RAM side would provide support for normal hi-res graphics in the 8-16K range, or would further mods have to be carried out to the circuit too, like a 10k resistor in the /WR line maybe? I've seen this in the standard RAMpack conversion mod and other internal RAM mods, but must confess to not understanding why it has to be there.

Sorry if these seem like dumb questions, but I'm having serious trouble wrapping my head around what constitutes 'hi-res compatibility' and how it translates to practical hardware... and it's not for want of reading. It just won't sink in. Any help is much appreciated.

[Andy Rea]

yep if you pick up the address lines from the intermal ram it'll do just fine for 'normal' Hi-res.

i'm too at a bit of a loss as to why the 10K resistor should be added, and have not got it on any of my zeddies, the only time i can even think you might want it, is if the cpu accepted a bus-request, it would then set the address bus, data bus, and most of the control lines to a high Z state.

the difference between the hi-res modes is mostly to do with the way that the zeddy creates the display, the pixels that make up the charatcter (or hi-res patterns) is fetched from a memorty location during the refresh phase of a (usually) forced NOP instruction by the ULA, as it happens during a z80 refresh cycle the address bus is loaded with the I (high byte) and R (low byte) registers, true hi-res manipulates the I and R registers so that it starts off pointing to the begining of the H-file (hi-res display file) incrementing with each NOP. in normal sinclair character mode, the lower 9 bytes of this address is replaced by the ULA, but these address lines only go to the ROM, so if you want to use CHR$ maps you need to use the ULA address lines, or some other clever trickery.

Andy

[Slipstreem]

Thanks, Andy. We seem to speak the same lingo when it comes to describing logic operation. Most of it went in on the first read with the rest following closely on the second. I just need to go and read up a little more on the registers, but your explanation should reduce my 'silly question' count significantly.

[VinCBR900]

There is a related thread that might be worth reviewing
viewtopic.php?t=66

Personally, if you are using a DIL chip (rather than individual tiny little logic SOT23) then it doesn matter which 14/16pin DIL, so I would prefer to build something with a bit more flexibility.
Wilf Rigter shows how to use an 8 to 1 decoder chip to allow selection from any 8k memory space. Installin a DIP switch and pullups then lets you shuffle the ram aroudn wherever you want.
http://www.user.dccnet.com/wrigter/inde ... XRAMIO.htm

However, If you are building from bits in the junk box, then same thing can be achieved with the worlds most popular decoder, the 74ls138. I tried to find a schematic with no joy, but Im sure Andy Rea has one somewhere, he has them for most things...

HTH, Vincent