I've borked it

[msknight]

Well, that turned out to be a problem... when I paired the vLA81 with the MyRetrostore RAM, it worked. When I replaced the RAM with the hm65256ap-15 chip, I came back to the white and black bars.

So as well as the dead ferranti, I have a RAM chip that doesn't want to work. Now... the question is... does that RAM chip need some sort of alteration for its speed or something.

I did draw a conclusion that because Mark recommended that chip, I thought it wouldn't need anything extra... but then I looked back at the conversation and I wondered whether Mark was just recommending the seller...
https://www.sinclairzxworld.com/viewtop ... 476#p53476

So I'm not sure whether there's something extra that needs to be done to that ram chip, to enable it to work.

[msknight]

The known good Ferranti doesn't want to work with this RAM either. Same white and black bars.

[msknight]

Confirmed - known good Ferranti works with MyRetrostore 16k ram.

There's something about these RAM chips, probably to do with timing, that doesn't want to work.

I don't think they played a part in the original ferranti dying, though... they just confused the troubleshooting process and sent me on a goose chase.

[siggi]

1.) Sinclair invested exactly nothing in decoupling capacatitors, but CMOS rams like them (typically 100 nF tantalum)
2.) There might be a well-known timing problem:
https://www.sinclairzxworld.com/viewtop ... 078#p39078

HTH Siggi

[msknight]

You may very well be right on that.

I'll wait to see what Mark has to say about it and if he has any other recommendations on how to go forward, before I enact what's in that other thread.

[1024MAK]

Yes, fitting extra 100nF multilayer ceramic capacitors (as close as possible to the power pins of the chip) is wise. But I'm not convinced this is the issue here. The ZX81 does have four 47nF ceramic capacitors, which given the size of the board, is at least something. C9, one of these four is near the RAM chip.

As to regards to timing issues, this is possible. But with most faster more modern SRAM chips, normal SLOW mode does work, even if the picture is affected.

I feel that somehow, there were multiple problems.

Mark

[msknight]

There were multiple problems, but now I am down to the RAM chip issue.

This is the only one that is left.

From what I can read from the picture of the half K chips, they are uPD2114LC with a -1 in the far edge. If I read those correctly, they are 300ns read and access time on the read cycle, write cycle and access time, with 150ns write time. So I might need a capacitor to run high res, but that isn't playing into the "data bus crash" that I'm seeing at the moment.

So... if I read things right, I need to bend up pin 22 and connect it to RD next. Yes?

[1024MAK]

No, if you make use of the /RD line, that messes up hi-res graphics.

With very slow RAM, it makes a difference if /OE and /CS (/CE) are controlled differently. But with 'normal speed' chips, the RAM chip should be fast enough that the chip will respond in plenty of time, hence no problem with /OE and /CS (/CE) being connected together and driven from the same signal (as standard in a ZX81).

For a 28 pin SRAM chip, pin 20 is /CS (/CE), pin 22 is /OE.

When we add a capacitor, that's to delay the chip from turning off it's outputs (so the data stays on the data bus for longer) rather than anything else.

The 2114 chips are normally types that have an access time of 300ns or better. This is different from the ZX80 which had a different requirement.

Mark

[msknight]

Ok - well, I'm not sure what to do now then. I'm at a dead end on getting these 1988 memory chips to work.

[1024MAK]

This is why I'm confused as well...

Mark