Sinclair ZX80 / ZX81 / Z88 Forums

1024MAK wrote: ↑Tue Feb 20, 2024 9:52 pm This is why I'm confused as well...

Mark

I'm comforted by not being alone then

Any other vintage chip suggestions which are known to work please? All of these are not working, so either these are fakes (the seller probably won't have known) or else there's something going on which would require someone with more knowledge to have hands on.

(Pseudo)static RAM chips can easily be tested with a retro chip tester.
I don't know who in the UK owns one and would offer to test your chips.
I have one but living in Germany postage would be ridiculous.

I've compared the Hitachi chip against the half K chip read cycles and it looks like /OE is doing nothing. Looks like the whole thing is driven by the /CE and I should instead tie /OE to ground?

Or do I have that wrong?

Paul wrote: ↑Wed Feb 21, 2024 5:54 am (Pseudo)static RAM chips can easily be tested with a retro chip tester.

I looked one up and a PCB for a tester is 30 euros, then I've got parts and assembly. For my purposes, it would be quite an expense. I have a small one for BBC Micro RAM chips, very simple design and very cheap... unfortunately won't work for these.

My learning has a few years to go before I'm capable of writing and wiring an arduino to test a chip. I'm still bumbling along.

I think this is most likely down to a wiring/timing issue, although there seem to be quite a bit of fake retro parts around these days.

msknight wrote: ↑Wed Feb 21, 2024 5:55 am I've compared the Hitachi chip against the half K chip read cycles and it looks like /OE is doing nothing. Looks like the whole thing is driven by the /CE and I should instead tie /OE to ground?

Or do I have that wrong?

This diagram shows a "Read Cycle (1) (/CE controlled)"
Maybe it has also a different "/OE controlled" mode?

Could you show diagrams of its "Write mode". That is the critical mode, where rubbish might be written into ram.

Siggi

msknight wrote: ↑Wed Feb 21, 2024 5:55 am I've compared the Hitachi chip against the half K chip read cycles and it looks like /OE is doing nothing. Looks like the whole thing is driven by the /CE and I should instead tie /OE to ground?

Or do I have that wrong?

Wrong.

/CE (/CS) when low selects the chip and if it has a lower power standby mode, 'wakes' it up. If /W (/WE) is high and /OE is high, it will not accept writes and will not drive the data bus.

If /OE is low at the same time as /CE (/CS) is low, it enables its data outputs. These being three state / tri-state outputs.

Yes, /OE could be connected to 0V/GND, but you don't gain anything, as normally the chips response to the /OE control input is quicker than that of the /CE (/CS) control input.

Some EEPROM/EPROM programmers can test SRAM chips like these. Although they may not test the access timing.

Mark

Oh good grief, there are two read and two write control modes. Urk.

https://www.alldatasheet.com/datasheet- ... 5256B.html

As I have already written in the other thread: bend the ram's pin /OE up and connect it to the Z80 /RD signal (e. g. at the edge connector).
That solves the timing problem during WRITE cycles ....

Siggi

siggi wrote: ↑Wed Feb 21, 2024 11:17 am As I have already written in the other thread: bend the ram's pin /OE up and connect it to the Z80 /RD signal (e. g. at the edge connector).
That solves the timing problem during WRITE cycles ....

Siggi

I did that. It didn't change anything, unfortunately.

When changing a processor, I accidentally bent pin 21, /RD. The resultant thick bands on the screen are the same I'm getting with the vintage ram issue, so I don't feel like a solution to this is far away. I just don't have the knowledge to be able to make that final jump.