zx80nut wrote:
The pull-ups perform two purposes
1. any address not handed by the rom or ram would always be read as FF.
2. TTL pull-ups are quite weak, which is why the logic 1 voltage is quite a bit lower than 5V. The pull-ups would help drag this voltage higher, especially as the data has passed through resistors, dropping the voltage lower.
1. This is a good idea in general but not needed for the ZX81 as RAM is not fully decoded and the same RAM is mirrored many times on different addresses.
So the RAM test is made not with check contents FF - its filled and after decremented its contents incremently and checked if memory was decremented before. This will show duplicated RAM addresses and memory test stops. Unused ROM would not help much because the ROM has to know which address is used by ROM and for what. FF wouldn't help this way.
2. As TTL allows voltage to be dropped down to 2,0 V (which is definetly treated as high, same way as 5,0 V) this is not necessary. I never heard that somebody used this to "improve" logic voltage as this would increase power consumption only and it really doesn't matter if voltage is 2,0 V or 3,5 V or 5,0 V. All voltage upper 2,0 V is definetly high. And too many or unused pullups would increase the output low voltage of TTL's.
The trick with the resistors is during video display routine.
* in the first 2 clock states of M1, ULA pulls down the databus to zero for executing nops instead of the real code (and during first clock state read the "code" in the display file.
* then in the next clock states (refresh cycle) the ULA uses the read char before to overload the address on the rom (here real addressbus from cpu is coupled off with the 1k resistor)
The databus of the CPU is in input mode during the first 2 clock states and after in tristate mode during refresh (or floating which is simply same as tristate).
The ULA databus is in input mode during first cycle, output mode (nop) during second cycle and input mode again during T3 and T4.
I think ROM CS is not fast enough to go high and low in between and deliver data within short 300ns - so its kept low and just the address changes for reading another address cell in ROM. So the ROM is not disturbed when showing NOPs to CPU while discoupled with 470R resistor - but can pull down databus low when cpu is in refresh cycle and databus floating and ULA databus is in input mode. So you have a voltage of 10k to 470R divisor of about 0,22 V which means low.
This is described more detailed here by Wilf Rigter:
http://www.user.dccnet.com/wrigter/inde ... torial.htm
As mentioned before, open collector outputs are used for switching different voltages than VCC for low voltage conversion of ICs with 3,3 V for example or high voltages. Tristate (or Z-state) is just for sharing a signal, mostly address and databus in modern computer systems. This is the way DMA is working in your PC (direct memory access) for fast transfer of data from disk to memory. The disk get the read command and the address where data has to be stored, reads internally data while CPU does something else more useful than waiting for data
and when the disk is ready to transfer it catches the bus through a signal (bus request), transfers data to memory itself and releases when finished. This is more quickly than let the cpu wait for data, read it first from disk to cpu and write it after from cpu to memory.
Back to the resistors in general for open collectors:
In principle you can drive the databus low without pullup resistors but this takes more time as Z80 input current is maybe only 5uA and you always have capacitors in input and open collector output. Let's say 5pF up to 10pF (input and output). 5uA has the same result like a 1MegOhm resistor and need 5 up to 10 us (microseconds) to get maybe low. But as it is clocked at high frequency you need more fast transistions. As you find in many datasheets, delay time is measured always with a defined (very low) resistor and capacitor (as you can not avoid capacitors in general).
As you find here
http://www.datasheetcatalog.org/datashe ... 209_DS.pdf for the 74LS00 - short delay of 3 to 10ns is defined with a 2k resistor and max. 15pF. For the open collector 74LS07 the resistor is defined with 110R for fast switching.
If you study transistor datasheets you will find that the maximum operating frequency is possible only at a defined minimum collector current and will decrease significantly for very low currents. This is always a decision of either fast switching or low power consumption. You can not have all.
http://www.datasheetcatalog.org/datashe ... yzqszz.pdf (See gain-bandwith product versus collector current)
It has nearly 300 (e.g. gain 30 at 10 MHz at 5 V) with 20mA collector current - but only about 35 (gain 3.5 at 10 MHz at 5V) at 0,1 mA.
PS: Okay - I know about newer HC, HCT families. This only as example for better understanding the basics for the thread opener.
