Let's hope the file size isn't an issue for maintainer(s?) of this site - it shouldn't be I think, as this is low-traffic material.
My design uses 59 macrocells from a 72 macrocell CPLD (Xilinx XC9572). So with a bit of luck it might fit in a 64 macrocell Altera CPLD. But that would be a tight fit. Unfortunately 128 macrocell Altera devices I know off, come in 100 pin QFP packages. Which is just a little too big to fit onto a 40p-DIP footprint (although Andy somehow managed that anyway ).Rink wrote:I wonder what the utilisation of the CPLD is like? I'd be tempted to see if I can put the design in an Altera CPLD since I've been playing with those lately.
ZX81 ULA logic isn't very complex - a few counters, a few flipflops, an 8 bit shift register, and some logic tying things together. Understanding how everything works together in a ZX81 is the hard part IMHO. A 64 macrocell will probably do if all you need is a 'vanilla' ZX81 ULA replacement. If you want to add extra's like clock doubling/tripling, a blockswitching mechanism for the RAM etc, then better go for a 128 macrocell device.
You'll also need 5V tolerant inputs, and personally I have a strong preference for not starting new designs using parts that are considered obsolete. So for this application I'd be looking at Xilinx 9500XL (XC9572XL in VQ64 package would be a nice choice), or Altera MAX 3000A family.