ZX81 ULA-in-a-CPLD

Any discussions related to the creation of new hardware or software for the ZX80 or ZX81
overCLK
Posts: 18
Joined: Wed Nov 07, 2018 10:12 pm
Location: Spain

Re: ZX81 ULA-in-a-CPLD

Post by overCLK » Sat Nov 10, 2018 4:55 pm

Andy Rea wrote:
Sat Nov 10, 2018 4:23 pm
if you have the ability to program eeprom, then you could write some test code, simple loops repeatedly turning on and off the nmi, see if that turns up anything useful on the logic analyser.
Yes, I can cook my own eeproms. I have made some custom ROMs before and the results were consistent (NMIs counted right, NMIs enabled and disabled with OUT commands,...). Can you think of another test that could be meaningful to troubleshoot the current situation?
Andy Rea wrote:
Sat Nov 10, 2018 4:23 pm
also.. the zx80 / 81 link... has a pullup resistor right ?
Yes it has. Nevertheless I understand that the only difference would be the number of NMI pulses (55 vs 31), but I'm right to think that the only difference should be some sync issues, but not the NMI being skipped?
Andy Rea wrote:
Sat Nov 10, 2018 4:23 pm
also try turning of bit-keeper ( i think thats whats its called ) and select float in the fitter options for the cpld iirc aint at that computer right now

regards andy
Hmm, interesting stuff. Will take a look to that (even when I currently don't know yet what it is) :-)

Thanks a lot!

Cheers
Manuel

User avatar
Andy Rea
Posts: 1506
Joined: Fri May 09, 2008 2:48 pm
Location: notts UK

Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Sat Nov 10, 2018 5:09 pm

bit keeper is a weak feedback inside the io buffer of the xilinx chip it will retain the last known logic level on inputs without sufficiently strong pull-up / downs.

i asked about the zx80 / zx81 link incase somehow the thing thinks its gone into zx80 mode.

as for meaningful tests with home brew code, try to reproduce events leading up to a failure.. yeah i know its a bit vague... sorry :cry:

regards andy
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

McKlaud
Posts: 204
Joined: Tue Dec 19, 2017 10:02 pm
Location: St Albans, UK

Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Sat Nov 10, 2018 7:17 pm

Gents, correct me if i am wrong, but there is no NMI generation at all when the ZX80_81 is pulled down. The quoted numer of 55 or 31 indicates how many scanlines should be generated and this value is read from ROM and held under the system variable called MARGIN. The MARGIN value is driven by the other ULA input called USA/UK. When this input is pull down, the MARGIN variable is loaded with value of 55, and when this input is pulled up we have UK version of Zeddy with 32 scanlines.
Claudius
----------

User avatar
Andy Rea
Posts: 1506
Joined: Fri May 09, 2008 2:48 pm
Location: notts UK

Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Sat Nov 10, 2018 8:38 pm

McKlaud wrote:
Sat Nov 10, 2018 7:17 pm
Gents, correct me if i am wrong, but there is no NMI generation at all when the ZX80_81 is pulled down. The quoted numer of 55 or 31 indicates how many scanlines should be generated and this value is read from ROM and held under the system variable called MARGIN. The MARGIN value is driven by the other ULA input called USA/UK. When this input is pull down, the MARGIN variable is loaded with value of 55, and when this input is pulled up we have UK version of Zeddy with 32 scanlines.
yes thats what i am trying to get at, if there is no pullup on the zx80 / 81 line then perhaps it is thinking its gone into zx80 mode.
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

McKlaud
Posts: 204
Joined: Tue Dec 19, 2017 10:02 pm
Location: St Albans, UK

Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Sat Nov 10, 2018 8:51 pm

well, this is not the case in my ULA, because I've got pull-ups and pull-downs there.
Claudius
----------

User avatar
Andy Rea
Posts: 1506
Joined: Fri May 09, 2008 2:48 pm
Location: notts UK

Re: ZX81 ULA-in-a-CPLD

Post by Andy Rea » Sat Nov 10, 2018 8:54 pm

McKlaud wrote:
Sat Nov 10, 2018 8:51 pm
well, this is not the case in my ULA, because I've got pull-ups and pull-downs there.
When you have eliminated the impossible, whatever remains, however improbable, must be the truth.

Sir Arthur Conan Doyle, stated by Sherlock Holmes.

strike that one then :) soon we will nail it down :lol:
6 x ZX81, 1 x TS1500 , 1 x +3e, 1 x timex 2040 printer, 1 x timex 2020 cassette deck, siclair printer and some spectrum

overCLK
Posts: 18
Joined: Wed Nov 07, 2018 10:12 pm
Location: Spain

Re: ZX81 ULA-in-a-CPLD

Post by overCLK » Sat Nov 10, 2018 8:56 pm

McKlaud wrote:
Sat Nov 10, 2018 7:17 pm
Gents, correct me if i am wrong, but there is no NMI generation at all when the ZX80_81 is pulled down. The quoted numer of 55 or 31 indicates how many scanlines should be generated and this value is read from ROM and held under the system variable called MARGIN. The MARGIN value is driven by the other ULA input called USA/UK. When this input is pull down, the MARGIN variable is loaded with value of 55, and when this input is pulled up we have UK version of Zeddy with 32 scanlines.
Sorry, I messed things up :-( . Of course US/UK is what controls the upper/bottom screen line count and ZX80_81 whether NMIs are produced or not. But I think it is 31 (USA) or 55 (UK).
Cheers.

McKlaud
Posts: 204
Joined: Tue Dec 19, 2017 10:02 pm
Location: St Albans, UK

Re: ZX81 ULA-in-a-CPLD

Post by McKlaud » Sat Nov 10, 2018 9:03 pm

Claudius
----------

overCLK
Posts: 18
Joined: Wed Nov 07, 2018 10:12 pm
Location: Spain

Re: ZX81 ULA-in-a-CPLD

Post by overCLK » Sat Nov 10, 2018 9:07 pm

Andy Rea wrote:
Sat Nov 10, 2018 8:38 pm
McKlaud wrote:
Sat Nov 10, 2018 7:17 pm
Gents, correct me if i am wrong, but there is no NMI generation at all when the ZX80_81 is pulled down. The quoted numer of 55 or 31 indicates how many scanlines should be generated and this value is read from ROM and held under the system variable called MARGIN. The MARGIN value is driven by the other ULA input called USA/UK. When this input is pull down, the MARGIN variable is loaded with value of 55, and when this input is pulled up we have UK version of Zeddy with 32 scanlines.
yes thats what i am trying to get at, if there is no pullup on the zx80 / 81 line then perhaps it is thinking its gone into zx80 mode.
Well, I just tested the zx80_81 pin with the analyzer to verify that it's all the time at high level. So it doesn't seem to be the issue.
Additionally I've burned a EEPROM with the ZX81 firmware and things are a bit different now:
- The NMI is still lost.
- But the HALT is still coming as if the screen was rendered, only the timing has changed and it's taking longer.
halt-no-nmi.png

overCLK
Posts: 18
Joined: Wed Nov 07, 2018 10:12 pm
Location: Spain

Re: ZX81 ULA-in-a-CPLD

Post by overCLK » Sat Nov 10, 2018 9:14 pm

McKlaud wrote:
Sat Nov 10, 2018 9:03 pm
https://problemkaputt.de/zxdocs.htm#zx8 ... laytimings - see there.
Strange, because:
- I see 55 NMI pulses with US_UK pulled up in my British Zeddy and 31 before adding the pull-up.
- I have seen this comment in ZX81 code disassembly (from here: https://www.tablix.org/~avian/spectrum/rom/zx81.htm) :

Code: Select all

;   This is a good time to test if this is an American or British machine.
;   The US machine has an extra diode that causes bit 6 of a byte read from
;   a port to be reset.

        RLA                     ; (4) compensate for the shift test.
        RLA                     ; (4) rotate bit 7 out.
        RLA                     ; (4) test bit 6.

        SBC     A,A             ; (4)           $FF or $00 {USA}
        AND     $18             ; (7)           $18 or $00
        ADD     A,$1F           ; (7)           $37 or $1F

;   result is either 31 (USA) or 55 (UK) blank lines above and below the TV 
;   picture.

Post Reply